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 

SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009

   

    

www.ti.com

FEATURES

2-MHz High Frequency Oscillator with 1-MHz

Operation Per Channel

D Matched Internal Slope Compensation

Circuits

D Programmable Maximum Duty Cycle Clamp

60% to 90% Per Channel

D Peak Current Mode Control with

Cycle-by-Cycle Current Limit

D Current Sense Discharge Transistor for

Improved Noise Immunity

D Accurate Line Under and Over-Voltage Sense

with Programmable Hysteresis

D Opto-Coupler Interface

D 110-V Internal Start-Up JFET (UCC28221)

D Operates from 12-V Supply (UCC28220)

D Programmable Soft-Start

APPLICATIONS

High Output Current (50-A to 100-A)

Converters

D Maximum Power Density Designs

D High Efficiency 48-V Input with Low Output

Ripple Converters

D High Power Offline, Telecom and Datacom

Power Supplies

DESCRIPTION

The UCC28220 and UCC28221 are a family of BiCMOS

interleaved dual channel PWM controllers. Peak

current mode control is used to ensure current sharing

between the two channels. A precise maximum duty

cycle clamp can be set to any value between 60% and

90% duty cycle per channel.

UCC28220 has an UVLO turn-on threshold of 10 V for

use in 12-V supplies while UCC28221 has a turn-on

threshold of 13 V for systems needing wider UVLO

hysteresis. Both have 8-V turn-off thresholds.

TYPICAL APPLICATION

UCC28221

VDD

CS1

SLOPE

CS2

CTRL

LINEOV

LINEUV

OUT1

OUT2

CHG

DISCHG

Bias

E/A

LINE

VIN

(+48V)

REF

GND

CS1

VOUT

REF

1/2 UCC27324

CS2

HYS

NOTE: Pin 16 is a no connect (N/C) on UCC28220 which does not include the JFET option.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (32 pages)

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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 FEATURES D 2-MHz High Frequency Oscillator with 1-MHz D D D D D D D D D APPLICATIONS D High Output Current (50-A to 100-A) Operation Per Channel Matched Internal Slope Compensation Circuits Programmable Maximum Duty Cycle Clamp 60% to 90% Per Channel Peak Current Mode Control with Cycle-by-Cycle Current Limit Current Sense Discharge Transistor for Improved Noise Immunity Accurate Line Under
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 DESCRIPTION (CONTINUED) Additional features include a programmable internal slope compensation with a special circuit which is used to ensure exactly the same slope is added to each channel and a high voltage 110-V internal JFET for easier startup for the wider hysteresis UCC28221 version. The UCC28220 is available in both 16-pin SOIC and low-profile TSSOP packages.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†} Parameter High voltage start-up input, VIN UCC2822X UNIT 110 V Supply voltage, VDD 15 V Output current (OUT1, OUT2) dc , IOUT(dc) ±10 mA OUT1/ OUT2 capacitive load 200 pF REF output current, IREF 10 mA Current sense inputs, CS1, CS2 −1.0 to 2.0 V Analog inputs (CHG, DISCHG, SLOPE, REF, CNTRL) −0.3 to 3.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS: VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to 105°C, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX 3.15 3.3 3.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS: VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to 105°C, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS Output Section (OUT1, OUT2) Low level IOUT = 10 mA IOUT = −10 mA, VREF – VOUT 0.4 1 High level 0.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 FUNCTIONAL BLOCK DIAGRAM REF RUN REFERENCE 14 16 VIN (N/C on UCC28220) UVLO/ JFET CONTROL P2 CHG 10 T OSC DISCHG 9 CLK1 Q FF + 4 VDD CLK2 Q CS1 3 CLK1 + S Q LATCH R 0.5 V VREF 13 OUT1 Q RUN 11 SLOPE COMPENSATION 0.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 Terminal Functions TERMINAL PIN NUMBER FUNCTION NAME I/O 2 LINEOV I Input for line over voltage comparator 2 3 LINEHYS I Sets line comparator hysteresis 3 4 VDD I Device supply input 4 4 5 CS1 I Channel 1 current sense input 5 5 6 SLOPE I Sets slope compensation 6 6 7 CS2 I Channel 2 current sense input 7 7 8 SS I Soft-start input 8 8 9 CTRL I Feedback control input 9 9 12 DISCHG I Sets os
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 CHG: A resistor from this pin to GND sets up the charging current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the DISCHG pin is used to set up the operating frequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V. DISCHG: A resistor from this pin to GND sets up the discharge current of the internal CT capacitor used in the oscillator.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION LINE Over Voltage and Under Voltage Three pins are provided to turn-off the output drivers and reset the soft-start capacitor when the converter input voltage is outside a prescribed range. The under-voltage set point and under-voltage hysteresis are accurately set via external resistors.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Input Voltage R1 UV 15 + 1.26 V 1.26 V + S1 OPEN HYS 2 R4 S2 CLOSED LINE_GOOD R2 OV 1 + R3 1.26 V Figure 1. Line UVLO and OVLO Functional Diagram ENABLE LINE_GOOD OFF V1 V2 V3 V4 Figure 2. Line UVLO and OVLO Operation VDD Because the driver output impedance is high the energy storage requirements on the VDD capacitor is low.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Reference For improved noise immunity it is recommended that the reference pin, REF, be bypassed with a minimum of 0.1uF of capacitance to GND. Oscillator Operation and Maximum Duty Cycle Setpoint The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is programmable over a 200 kHz to 2MHz frequency range with 20% to 80% maximum duty cycle range.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION VDD 13 V 13 V 8 − 14 V 10 V NORMAL OPERATION 8 V (UVLO off) 0V OUTx GATE DRV OFF ON ON HV JFET OFF Figure 3. JFET Device Operation with VDD Voltage Soft-Start A current is forced out of the SS pin, equal to 3/7 of the current set by RCHG, to provide a controlled ramp voltage. The current set by the RCHG resistor is equal to 2.5 V divided by RCHG.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Slope Compensation The slope compensation circuit in the UCC28220/1 operates on a cycle-by-cycle basis. The two channels have separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing is unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that channel’s output is off.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Determining the value for the slope compensation resistor: Design Example: NCT(p) = 1 VOUT = 12 LOUT = 3.2 x 10 −6 NCT(s) = 50 Np = 7 RSENSE = 5.23 Ns = 5 VEA(cl) = 1.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 TYPICAL APPLICATION CIRCUITS VIN CS1 UCC28221 1 OV VIN 16 2 HYS UV 15 3 VDD REF 14 Bias VOUT 1/2 UCC27424 4 CS1 OUT1 13 5 SLOPE OUT2 12 CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL DISCHG 9 1/2 UCC27424 REF E/A Figure 5. Interleaved Flyback Application Circuit Using the UCC28221 www.ti.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 VIN CS1 UCC28220 1 OV 2 HYS UV 15 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 N/C 16 Bias 1/2 UCC27424 VOUT CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL 1/2 UCC27424 DISCHG 9 E/A Figure 6. Interleaved Boost Application Circuit Using the UCC28220 16 www.ti.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs SUPPLY VOLTAGE UVLO THRESHOLDS vs TEMPERATURE 4.0 13.5 3.5 11.5 UCC28220 UVLO on threshold and UCC28221 JFET on threshold (when not switching) 10.5 9.5 8.5 UCC28221 EXCLUDES JFET CURRENT 3.0 2.5 2.0 1.5 1.0 UCC28220 and UCC28221 UVLO off threshold and UCC28221 JFET on threshold (when switching) 0.5 7.5 0.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 TYPICAL CHARACTERISTICS LINEOV AND LINEUV THRESHOLDS vs TEMPERATURE SLOPE COMPENSATION vs TEMPERATURE 1.270 230 225 LINEOV 1.260 Vth − Trip Threshold − V SLOPE − Slope Compensation − mV per µs 1.265 1.255 1.250 LINEUV 1.245 1.240 1.235 1.230 RSLOPE = 75 kΩ 220 215 210 205 CS1 = 0 V 200 195 190 CS1 = 0.5 V 185 180 175 170 −50 −25 0 25 50 75 100 125 −50 Tj − Temperature − °C −25 0.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 TYPICAL CHARACTERISTICS RISE AND FALL TIME vs TEMPERATURE (CL = 50 pf) VOH AND VOL vs TEMPERATURE 1.0 0.9 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOUT = 10 mA 0.8 VO -Output Voltage − V Tr and Tf − Rise and Fall Time − ns 20 19 18 17 Fall Time Rise Time 0.7 VREF − VOUT (VOH) 0.6 0.5 0.4 VOL 0.3 0.2 0.1 −50 −25 0 25 50 75 100 0.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 TYPICAL CHARACTERISTICS PROGRAMMING RESISTORS vs SWITCHING FREQUENCY OSCILLATOR FREQUENCY vs TEMPERATURE 1M 550 RCHRG = RDISRG = 10.
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SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Related Products DEVICE DESCRIPTION PACKAGE OPTION UCC27323/4/5 Dual 4-A High Speed Low Side MOSFET Drivers SOIC-8, PowerPAD MSOP-8, PDIP-8 UCC27423/4/5 Dual 4-A High Speed Low Side MOSFET Drivers with Enable SOIC-8, PowerPAD MSOP-8, PDIP-8 TPS2811/12/13 Dual 2.4-A High Speed Low Side MOSFET Drivers SOIC-8, TSSOP-8, PDIP-8 UC3714/15 Dual 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC28220DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC28220PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28220DR SOIC D 16 2500 367.0 367.0 38.0 UCC28220PWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.