Datasheet
SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005
20
www.ti.com
APPLICATION INFORMATION
The selection process begins with the selection of R1 so that the peak I
AC
current at high ac line is about 500 µA,
see Table 2. Second, select R15 for the minimum VFF voltage, also shown in Table 2. Third, select C8, in Table
2, to average the VFF voltage with sufficiently low ripple to meet a third harmonic distortion budget. For a system
with a 3% THD target, it is typical to allow the feedforward circuit to contribute 1.5% third harmonic distortion
to the input waveform [4]. An attenuation factor of 0.022 will meet the criteria. Finally, select the MOUT resistor
in Table 2, R12, so that the voltage across R12 equals the voltage across sense resistor R2 under the condition
of maximum power, minimum ac line voltage (V
VFF,
MIN
), and VAOUT at its maximum level of 5 V. Experimentally,
the multiplier output resistor, R12, may need to be increased slightly if the energy storage capacitor voltage sags
under maximum load. This would be due to tolerances in the components and the multiplier. In order to minimize
current amplifier offsets, set the value of the resistor on the ISENSE1 pin, R8, equal to the value of R12 as shown
in in Table 2.
Table 2.
REFERENCE
DESIGNATOR
EQUATION NOTES
R1
2
Ǹ
V
AC(max)
I
IAC(peak)
set i
IAC(peak)
+ 500 mA
R15
2 R1
V
VFF(avgmin)
V
AC(min) 0.9
set V
VFF(avgmin)
+ 1.4 V
C8
1
2 p f
AC
A
FF(2)
R15
A
FF(2)
+ 0.022 for 3% THD
R12
I
pk
R1 R2 k
ǒ
V
FF(min)
Ǔ
2
2
Ǹ
V
AC(min)
ǒ
V
VAOUT(max)
* 1V
Ǔ
k = 1/V
V
AC(min)
= minimum RMS input voltage
V
VFF(min)
= 1.4V
V
VAOUT(max)
= 5.0V
R8
R12
Always change R8 if R12 is changed
PFC current loop control
This controller uses average current loop control for the PFC stage. The current control loop must typically be
fast enough to track the rectified sinusoidal ac line voltage. There are many ways to design a controller that will
stabilize the PFC current loop. The method that is described here achieves good results for most applications.
[5]
This method assumes that both the natural frequency of the system and the zero of the linearized boost PFC
are much lower than both the switching frequency and the desired crossover frequency, f
CO(pfc)
, as described
in equation 12. The left side of the inequality in equation 12 will usually be true since the capacitance of C1 is
quite large.
1 * D
PWM(min)
L1 C1
Ǹ
and
2P
IN
C1 V
C1
2
tt 2 p f
CO(pfc)
tt 2 p f
S(pfc)
(12)