Datasheet
8
5
VCC
GND
UCC28051
C
VCC
0.1 mF
C
BULK
2
4
8
6
STATUS
VDD
FB
GND
UCC28600
R
ST1
R
ST2
R
CS
C
VDD
Primary Secondary
10 V
TL431
Feedback
M1
Q1
To Zero
Current
Detection
M2
R
VCC
C
BIAS
R
SU
N
B
N
P
N
S
D
Z1
D
BIAS
D
VDD
UCC28600
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SLUS646J –NOVEMBER 2005– REVISED JULY 2011
Fault Logic
Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides
the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are
implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected
in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.
Refer to the fault logic diagram in Figure 8 and the QR detect diagram in Figure 7 to program line OVP and load
OVP. To program the load OVP, select the R
OVP1
– R
OVP2
divider ratio to be 3.75 V at the desired output
shut-down voltage. To program line OVP, select the impedance of the R
OVP1
– R
OVP2
combination to draw 450
μA when the V
OVP
is 0.45 V during the ON-time of the power MOSFET at the highest allowable input voltage.
Oscillator
The oscillator, shown in Figure 5, is internally set and trimmed so it is clamped by the circuit in Figure 5 to a
nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB
voltage tries to drive operation to less than 40 kHz, the converter operates in green mode.
Status
The STATUS pin is an open drain output, as shown in Figure 8. The status output goes into the OFF-state when
FB falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin
is used to control bias power for a PFC stage, as shown in Figure 9. Key elements for implementing this function
include Q
ST
, R
ST1
and R
ST2
, as shown in the figure. Resistors R
ST1
and R
ST2
are selected to saturate Q
ST
when it
is desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and
R
ST1
causes Q
ST
to turn-OFF, thus saving bias power. If necessary, use a zener diode and a resistor (D
Z1
and
R
CC
) to maintain V
CC
in the safe operating range of the PFC controller. Note the D
VDD
- C
VDD
combination is in
addition to the standard D
BIAS
- C
BIAS
components. This added stage is required to isolate the STATUS circuitry
from the startup resistor, R
SU
, to ensure there is no conduction through STATUS when VDD is below the UVLO
turn-on threshold.
Figure 9. Using STATUS for PFC Shut-Down During Green Mode
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