Datasheet

UCC28600
www.ti.com SLUS646J –NOVEMBER 2005– REVISED JULY 2011
Cycle-by-Cycle Power Limit
The cycle terminates when the CS voltage plus the power limit offset exceeds 1.2 V.
In order to have power limited over the full line voltage range of the QR Flyback converter, the CS pin voltage
must have a component that is proportional to the primary current plus a component that is proportional to the
line voltage due to predictable switching frequency variations due to line voltage. At power limit, the CS pin
voltage plus the internal CS offset is compared against a constant 1.2-V reference in the PWM comparator. Thus
during cycle-by-cycle power limit, the peak CS voltage is typically 0.8 V.
The current that is sourced from the OVP pin (I
LINE
) is reflected to a dependent current source of ½ I
LINE
, that is
connected to the CS pin. The power limit function can be programmed by a resistor, R
PL
, that is between the CS
pin and the current sense resistor. The current, I
LINE
, is proportional to line voltage by the transformer turns ratio
N
B
/N
P
and resistor R
OVP1
. Current I
LINE
is programmed to set the line over voltage protection. Resistor R
PL
results
in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper amount
of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that R
CS
, R
PL
, R
OVP1
and
R
OVP2
must be adjusted as a set due to the functional interactions.
Current Limit
When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS
pin, the device initiates a shutdown. Retry occurs after a UVLO
OFF
/UVLO
ON
cycle.
Over-Voltage Protection
Line and load over voltage protection is programmed with the transformer turn ratios, R
OVP1
and R
OVP2
. The OVP
pin has a 0-V voltage source that can only source current; OVP cannot sink current.
Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative,
during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that
is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The
Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450 μA.
Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive,
during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is
greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLO
OFF
/UVLO
ON
cycle.
Undervoltage Lockout
Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout
(UVLO) always monitors VDD to prevent operation below the UVLO threshold.
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