Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers SOIC 16

 

 



SLUS542F − OCTOBER 2003 − REVISED JULY 2009



   

www.ti.com

FEATURES

Low Output Jitter

D Soft−Stop Shutdown of MAIN and AUX

D Ideal for Active Clamp/Reset Forward,

Flyback Converters

D Provides Complementary Auxiliary Driver

with Programmable Deadtime (Turn-On

Delay) between AUX and MAIN Switches

D Peak Current-Mode Control with

Cycle-by-Cycle Current Limiting

D 110-V Input Startup Regulator on UCC2891/3

D TrueDrivet 2-A Sink, 2-A Source Outputs

D Accurate Line UV and Line OV Threshold

D Programmable Slope Compensation

D 1.0-MHz Synchronizable Oscillator

D Precise Programmable Maximum Duty Cycle

D Programmable Soft Start

APPLICATIONS

150-W to 700-W SMPS

D High-Efficiency, Low EMI/RFI Off-Line or

DC/DC Converters

D Server, 48-V Telecom, Datacom

D High Power Adapter, LCD-TV and PDP-TV

DESCRIPTION

The UCC2891/2/3/4 family of PWM controllers is

designed to simplify implementation of the various

active clamp/reset switching power topologies.

The UCC289x is a peak current-mode, fixed-

frequency, high-performance pulse width modulator.

It includes the logic and the drive capability for the

auxiliary switch with a simple method of

programming the critical delays for proper active

clamp operation.

The UCC2891/3 includes a 110-V start-up

regulator for initial start-up and to provide

keep-alive power during stand-by.

Additional features include an internal

programmable slope compensation circuit,

precise D

MAX

limit, and a single resistor

programmable synchronizable oscillator. An

accurate line monitoring function also programs

the converter’s ON and OFF transitions with

regard to the bulk input voltage. Along with the

UCC2897, this UCC289x family allows the power

supply designer to eliminate many of the external

components, reducing the size and complexity of

the design.

RDEL

RTON

RTOFF

SYNC

LINE UV

OUT

AUX

PGND

4 VREF

VIN

UCC2891

6 GND

7CS

8 RSLOPE

14VDD

SS/SD

SECONDARY

SIDE E/A

LOAD

DRIVE

BIAS

WINDING

+VIN

DEL

OFF

SLOPE

VREF

BIAS

AUX

CLAMP

BULK

OUT

AUX

  ! " #$%! "  &$'(#! )!%*

)$#!" # ! "&%##!" &% !+% !%"  %," "!$%!"

"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%

!%"!/  (( &%!%"*

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (41 pages)

PAGE 1
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FEATURES D Low Output Jitter D Soft−Stop Shutdown of MAIN and AUX D Ideal for Active Clamp/Reset Forward, D D D D D D D D D DESCRIPTION The UCC2891/2/3/4 family of PWM controllers is designed to simplify implementation of the various active clamp/reset switching power topologies.
PAGE 2
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 THERMAL RESISTANCE INFORMATION PACKAGE THERMAL RESISTANCE SOIC−16 (D) TSSOP−16 (PW) θjc 36.9 to 38.4 θja (0 LFM) 73.1 to 111.6 θjc 33.6 to 35.0 θja (0 LFM) 108.4 to 147.
PAGE 4
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference VREF TJ = 25°C 0 A < IREF < 5 mA, 4.85 5.00 5.15 4.75 5.00 5.
PAGE 5
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.
PAGE 6
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL BLOCK DIAGRAM TYP: VREF = 5.0 V VREF 0.05 * IRDEL 1/2 x VREF 0.05 * IRDEL IRDEL RDEL 92/94 VREF CLOCK UV 1−DMAX OUT VDD 13 OUT 12 AUX 11 PGND 10 SS/SD + PWM OFF IRTON CT VDD 4 14 VDD OK 1.27 V VDD 1/2 x VREF VREF LINEUV 91/93 13 V/ 8 V 3 15 1.27 V + 2 RTOFF VIN (UCC2891/3) LINEOV (UCC2892/4) + OV 1 1/2 x VREF RTON 16 VREF SYNC IRDEL VDD OUT REF GEN PWM Offset 0.
PAGE 7
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TERMINAL FUNCTIONS TERMINAL UCC2891 UCC2893 UCC2892 UCC2894 I/O AUX 12 12 O This output drives the auxiliary clamp MOSFET which is turned on when the main PWM switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-on current and 2-A sink turn-off current.
PAGE 8
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS RDEL (pin 1) This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND (pin 6) sets the turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX (pin 14) is turning off and OUT (pin 13) is turning on.
PAGE 9
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) SYNC (pin 5) This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running frequency of the onboard oscillator ǒT SYNC t T SWǓ.
PAGE 10
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) FB (pin 9) This pin is an input for the control voltage of the pulse width modulator of the UCC2891 family. The control voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage reference and employing the compensation for the voltage regulation loop.
PAGE 11
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) OUT (pin 13) This high-current output drives an external N-channel MOSFET. Each controller in the UCC2891 family uses active high drive signals for the main switch of the converter. Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance of the external circuit components connected to these pins should be carefully minimized.
PAGE 12
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VIN (pin 16 − UCC2891 and UCC2893 only) The UCC2891 and UCC2893 controllers are equipped with a high voltage, P-channel JFET start up device to initiate operation from the input power source of the converter in applications where the input voltage does not exceed the 110-V maximum rating of the start up transistor.
PAGE 13
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION JFET Control and UVLO The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power consumption of the of the control circuit which also includes the gate drive power loss of the two power switches of an active clamp converter exceeds the current and thermal capabilities of the device.
PAGE 14
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION As the controller starts operation it draws its bias power from the CBIAS capacitor until the bootstrap winding takes over (refering to Figure 12). During this time VDD voltage is falling rapidly as the JFET is already off but the bootstrap voltage is still not sufficient to power the control circuits.
PAGE 15
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOFF VIN V CLAMP, MAX VCLAMP VSS TSW OUT AUX Figure 3. Line Undervoltage Shutdown Waveforms, P−Channel To eliminate this potential hazard the UCC289x controllers safely discharge the clamp capacitor during power down. The AUX and OUT output continues switching while the soft-start capacitor CSS is being slowly discharged.
PAGE 16
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOVP VOVH VIN VSS OUT AUX UDG−03150 Figure 4. Line Overvoltage Sequence, P−Channel Pulse Skipping During output load current transients or light load conditions most PWM controllers needs to be able to skip some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily to the main switch, this would apply the clamp voltage across the transformer continuously.
PAGE 17
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION Synchronization The UCC2891 family has a synchronization input pin which can be used to synchronize their oscillator to a constant frequency system clock. The synchronization signal must have a higher frequency than the free running oscillator frequency and can be either in-phase or out-of-phase for interleaved operation.
PAGE 18
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION When a wider than ǒ1 * D MAXǓ T SYNC pulse is connected to the SYNC input, the oscillator is not able to maintain the maximum duty cycle, originally set by the timing resistor ratio (RON, ROFF). Furthermore, the timing capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram.
PAGE 19
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE The UCC2891 family offers a highly integrated feature set and excellent accuracy to control an active clamp forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design procedure. Refer to Figure 7 setup diagrams for component names.
PAGE 20
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Note, that tSS defines a time interval to reach the maximum current capability of the converter and not the time required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme does not allow accurate control over the ramp up time of the output voltage.
PAGE 21
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Step 5. Input Voltage Monitoring The input voltage monitoring functions is governed by the following two expressions of the voltage at the LINEUV terminal (pin 15): R IN2 at turn on, and R IN1 ) R IN2 V LINEUV + V ON V LINEUV + ǒ Ǔ V OFF * V VON ) I HYST R IN1 R IN2 at turn off. (19) (20) Since VON and VOFF are given by the power supply specification, VLINEUV equals the 1.
PAGE 22
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE In the UCC289x controllers, slope compensation is implemented by sourcing a linearly increasing current at the CS pin. When this current passes through the current sense filter resistor (RF), it is converted to a slope compensation ramp which can be characterized by its ǒdV SńdtǓ.
PAGE 23
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION The UCC2891 family of controllers is dedicated to control current mode active clamp flyback or forward converters in an isolated power supply. The key advantage of the active clamp topologies is the zero voltage switching (ZVS) of the primary side semiconductors.
PAGE 24
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION Figure 9 shows an active clamp forward converter with high-side clamp utilizing a P-channel auxiliary switch. Detailed analysis and design examples of active clamp converters are published in the references listed at the end of this datasheet. Gate Drive Implementations Both topologies can make use of either the high-side or the low-side clamp arrangement.
PAGE 25
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across the bootstrap winding equals the input voltage times the turns ratio.
PAGE 26
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases, the bias voltages are proportional to the output voltage.
PAGE 27
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 + + + + ADDITIONAL APPLICATION INFORMATION Figure 14. UCC2891 EVM Schematic www.ti.
PAGE 28
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS UVLO VOLTAGE THRESHOLDS vs JUNCTION TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 2.5 12 UVLO On IDD − Supply Current − mA VUVLO − UVLO Voltage Thresholds − V 14 10 8 UVLO Off 6 UVLO Hysteresis 4 2.0 1.5 1.0 0.
PAGE 29
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS VTH − Line Thresholds − V 1.28 1.26 1.24 1.22 1.20 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 15 Softstart Discharge Current 10 5 0 −5 −10 −15 −20 −50 125 Softstart Charge Current −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 20 Figure 19 SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs PROGRAMMING RESISTANCE 10 M 0.60 0.
PAGE 30
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE 74 275 RON = ROFF = 75 kΩ RON = ROFF = 75 kΩ 73 265 DMAX− Maximum Duty Cycle − % fSW − Switching Frequency − kHz 270 260 255 250 245 240 235 71 70 69 68 67 230 225 −50 72 −25 0 25 50 75 100 TJ − Junction Temperature − °C 66 −50 125 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 23
PAGE 31
SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS DELAY TIME vs DELAY RESISTANCE OUT AND AUX RISE AND FALL TIME vs JUNCTION TEMPERATURE 25 800 CLOAD = 2 nF 700 t DEL1 600 15 tDEL− Delay Time − ns tR/tF − Rise and Fall Times − ns Rise Time 20 Fall Time 10 t DEL2 500 400 300 200 5 100 0 −50 0 −25 0 25 50 75 100 TJ − Junction Temperature − °C 0 125 10 20 30 40 50 60 70 RDEL − Delay Resistance − kΩ Figure 28 Figure 27 DELAY TIME v
PAGE 32
PACKAGE OPTION ADDENDUM www.ti.
PAGE 33
PACKAGE OPTION ADDENDUM www.ti.
PAGE 34
PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 35
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 UCC2891DR SOIC D 16 2500 330.0 16.4 6.5 UCC2891PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2892DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 36
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2891DR SOIC D 16 2500 333.2 345.9 28.6 UCC2891PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2892DR SOIC D 16 2500 333.2 345.9 28.6 UCC2892PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2893DR SOIC D 16 2500 333.2 345.9 28.6 UCC2893PWR TSSOP PW 16 2000 367.0 367.0 35.
PAGE 37
PAGE 38
PAGE 39
PAGE 40
PAGE 41
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.