UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com DESCRIPTION (CONT.) The UCC28950 also offers multiple light-load management features including burst mode and dynamic SR on/off control when transitioning in and out of Discontinuous Current Mode (DCM) operation, ensuring ZVS operation is extended down to much lighter loads.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from the Typical Application Diagram.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from the Typical Application Diagram.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from the Typical Application Diagram.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com DEVICE INFORMATION Plastic 24-pin TSSOP (PW) UCC28950 1 VREF GND 24 2 EA+ VDD 23 3 EA- OUTA 22 4 COMP OUTB 21 5 SS/EN OUTC 20 6 DELAB OUTD 19 7 DELCD OUTE 18 8 DELEF OUTF 17 9 TMIN SYNC 16 10 RT CS 15 11 RSUM 12 DCM ADEL 14 ADELEF 13 TERMINAL FUNCTIONS TERMINAL I/O FUNCTION NUMBER NAME 1 VREF O 5-V, ±1.5%, 20-mA reference voltage output. 2 EA+ I Error amplifier non-inverting input.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Functional Block Diagram ADEL 14 VDD UVLO COMP VDD Thermal Shutdown VDD 23 EN + + 7.3 V Rise - 6.7 V Fall VREF 1 COMP 4 EA- 3 EA+ 2 22 OUTA Reference Generator Programmable Delay AB VDD ON/OFF 5V LDO DELAB 21 OUTB 20 OUTC PWM COMP + + + Programmable Delay CD Logic Block Lower "+" Input is Dominant 6 CLK 7 DELCD 19 OUTD Oscillator RT 10 RAMP 2.8 V 0.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Startup Timing Diagram No output delay shown, COMP-to-RAMP offset not included. 2 VP-P F E D C B A TMIN COMP RAMP PWM Add 0.85 V offset to RAMP No PWM pulses shorter than TMIN except during cycle-by-cycle current limit PWM TMIN SS > 0.5 V, then release COMP, DCM, CS , Outputs A,B,C,D,E and F CLK TMIN 4.8-V rise, 4.6-V fall VREF VREF_GOOD VDD 7.3-V rise, 6.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Steady State/Shutdown Timing Diagram No output delay shown, COMP-to-RAMP offset not included. VDD failed and VDD_GOOD goes low, Everything is shutdown 7.3V rise, 6.7V fall VDD VDD_GOOD 4.8V rise, 4.6V fall VREF VREF_GOOD TMIN CLK TMIN Add 0.85V offset to RAMP COMP 2Vp-p RAMP PWM No PWM pulses shorter than TMIN except during cycle-by-cycle current limit A B C D E F Figure 3.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com DETAILED PIN DESCRIPTION AND PARAMETER SETTINGS Start-Up Protection Logic Before the UCC28950 controller will start up, the following conditions must be met: • VDD voltage exceeds rising UVLO threshold 7.3 V typical. • The 5-V reference voltage is available. • Junction temperature is below the thermal shutdown threshold of 140°C. • The voltage on the soft-start capacitor is not below 0.55 V typical.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Soft Start and Enable (SS/EN) The soft-start pin SS/EN is a multi-function pin used for the following operations: • Closed loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady state duty cycle required by the regulated output voltage. • Setting hiccup mode conditions during cycle-by-cycle over current limit. • On/off control for the converter.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL)) The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and another output going high Figure 4. OUTA (OUTC) TABSET2 TABSET2 TCDSET2 TCDSET2 TABSET1 TABSET1 TCDSET1 TCDSET1 OUTB (OUTD) Figure 4.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com The delay time TABSET is defined by the following Equation 3. æ ö 5 ´ R AB TABSET = ç ÷ ns + 5ns è 0.15 V + CS ´ K A ´ 1.46 ø (3) The same equation is used to define the delay time TCDSET in another leg except RAB is replaced by RCD. æ ö 5 ´ RCD TCDSET = ç ÷ ns + 5ns è 0.15 V + CS ´ K A ´ 1.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com RA and RAHI define the portion of voltage at pin CS applied to the pin ADEL (See Typical Application Diagram). KA defines how significantly the delay time depends on CS voltage. Ka varies from 0, where ADEL pin is shorted to ground (RA = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (RAH = 0).
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)) The resistor REF from the DELEF pin to GND along with the resistor divider RAEFHI from CS pin to ADELEF pin and RAEF from ADELEF pin to GND sets equal delays TAFSET and TBESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 7. OUTA (OUTB) OUTD (OUTC) TAFSET1 TBESET1 OUTF (OUTE) TAFSET2 TBESET2 Figure 7.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com The plots in Figure 8 and Figure 9 show delay time settings as function of CS voltage and KEF for two different conditions: REF = 13 kΩ (Figure 8) and REF = 90 kΩ (Figure 9) TIME DELAY (TEF = REF = 13 kW) vs CS VOLTAGE 350 TAFSET, TBESET - Time Delay - ns 300 250 KA = 0.00 KA = 0.25 200 KA = 0.50 KA = 0.75 150 KA = 0.90 KA = 1.00 100 50 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 CS Voltage - V Figure 8.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Minimum Pulse (TMIN) The resistor RTMIN from TMIN pin to GND sets fixed minimum pulse TMIN applied to the output rectifier enabling ZVS of the primary switches at light load. If the output PWM pulse demanded by the feedback loop is shorter than TMIN, then controller proceeds to the burst mode of operation where even number of TMIN pulses are followed by the off time dictated by the feedback loop.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Switching Frequency Setting (RT) Connecting an external resistor RT between the RT pin and VREF pins sets the fixed frequency operation and configures the controller as a master providing synchronization output pulses at SYNC pin with 0.5 duty cycle and frequency equal to the internal oscillator.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Slope Compensation (RSUM) Slope compensation is the technique that adds additional ramp signal to the CS signal and applied to the: • Input of PWM comparator in case of peak current mode control. • Input of cycle-by-cycle current limit comparator. This prevents sub-harmonic oscillation at D > 50% (some publications suggest it might happen even at D < 50%).
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com If the resistor from RSUM pin is connected to VREF pin, then the controller operates in voltage mode control, still having the slope compensation added to CS signal used for cycle-by-cycle current limit. In such a case the slope is defined by the following Equation 13. æ (V - 2.5 V) ö V me = ç REF ÷ è 0.5 ´ RSUM ø ms (13) In Equation 12 and Equation 13, the VREF is in volts, RSUM is in kΩ, and me is in V/µs.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Dynamic SR ON/OFF Control (DCM Mode) The voltage at the DCM pin provided by the resistor divider Rdcmhi between VREF pin and DCM, and Rdcm from DCM pin to GND, sets the percentage of 2-V current limit threshold for the Current Sense pin, (CS). If the CS pin voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving mode, and shuts down the synchronous rectifiers, OUTE and OUTF.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com There is a nominal 20-µA switched current source used to create hysteresis. The current source is active only when the system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when being in DCM region, the DCM threshold is the voltage divider plus ΔV explained in Equation 14 below. When being in CCM region, the threshold is the voltage set by the resistor divider.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Current Sensing (CS) The signal from current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light-load efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time for outputs OUTE, OUTF. Connect the current sense resistor RCS between CS and GND.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest operation time during the cycle-by-cycle current limit which is defined as: TCL(on _ master ) = TCL(on _ slave) = CSS ´ (4.65 V - 3.7 V ) 20 mA (17) CSS ´ (4.65 V - 3.7 V ) 25 mA (18) Thus, if the soft-start capacitor CSS = 100 nF is selected, then the TCL(on) time will be 5 ms.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Synchronization (SYNC) The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as Master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF) • • • • • • All MOSFET control outputs have 0.2-A drive capability. The control outputs are configured as P-MOS and N-MOS totem poles with typical RDS(on) 20 Ω and 10 Ω accordingly. The control outputs are capable of charging 100-pF capacitor within 12 ns and discharge within 8 ns. The amplitude of output control pulses is equal to VDD.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Supply Voltage (VDD) Connect this pin to bias supply from 8 V to 17 V range. Place high quality, low ESR and ESL, at least 1-µF ceramic bypass capacitor CVDD from this pin to GND. It is recommended to use 10-Ω resistor in series to VDD pin to form RC filter with CVDD capacitor. Ground (GND) All signals are referenced to this node. It is recommended to have a separate quite analog plane connected in one place to the power plane.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS UVLO THRESHOLDS vs TEMPERATURE UVLO HYSTERESIS vs TEMPERATURE 640 UVLO - Under Voltage Lockout Hysteresis - mV UVLO - Under Voltage Lockout Thresholds - V 7.6 UVLO_RTH 7.4 7.2 7.0 UVLO_FTH 6.8 6.6 6.4 630 620 UVLO_HYST 610 600 590 580 6.2 -40 25 125 -40 TJ - Temperature - °C 125 TJ - Temperature - °C Figure 23. Figure 24. SUPPLY CURRENT vs TEMPERATURE STARTUP CURRENT vs TEMPERATURE 250 3.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VOLTAGE REFERENCE (VDD = 12 V) vs TEMPERATURE LINE VOLTAGE REGULATION (ILOAD = 10 mA) vs TEMPERATURE 5.010 5.001 ILOAD = 10 mA 5.000 ILOAD = 1 mA 4.995 ILOAD = 10 mA 4.990 4.985 VREF _ 10 mA _ 12 VDD 4.999 VREF - Line Voltage Regulation - V VREF - Voltage Reference - V 5.005 ILOAD = 20 mA 4.980 4.997 VREF _ 10 mA _ 10 VDD 4.995 4.993 4.991 VREF _ 10 mA _ 8 VDD 4.989 4.975 4.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) MAXIMUM SWITCHING FREQUENCY vs TEMPERATURE NOMINAL SWITCHING FREQUENCY vs TEMPERATURE 1079 FSW(max) - Maximum Switching Frequency - Hz FSW(nom) - Nominal Switching Frequency - Hz 95.4 95.0 94.6 94.0 1059 1039 1019 999 93.6 -40 -40 125 25 25 125 TJ - Temperature - °C TJ - Temperature - °C Figure 31. Figure 32. ERROR AMPLIFIER OFFSET VOLTAGE vs TEMPERATURE 0.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) ISS CHARGE CURRENT vs TEMPERATURE SHUTDOWN/RESTART/RESET THRESHOLD vs TEMPERATURE 26.0 VSS(std) - Shutdown/Restart/Reset Threshold - V 0.60 ISS - Charge Current - mA 25.5 25.0 24.5 24.0 23.5 0.55 0.50 0.45 0.40 0.35 0.30 -40 125 25 -40 TJ - Temperature - °C 25 125 TJ - Temperature - °C Figure 35. Figure 36. SS PULL-UP THRESHOLD vs TEMPERATURE SS CLAMP VOLTAGE vs TEMPERATURE 4.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CURRENT SENSE CYCLE-BY-CYCLE LIMIT vs TEMPERATURE CURRENT SENSE PROPAGATION DELAY vs TEMPERATURE 110 TCS(prop) - Current Sense Propagation Delay - ns VCS(lim) - Current Sense Cycle-By-Cycle Limit - V 1.996 1.994 1.992 1.990 1.988 1.986 1.984 107 104 101 98 95 -40 125 25 -40 TJ - Temperature - °C 125 TJ - Temperature - °C Figure 39. Figure 40.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUTS SOURCE RESISTANCE vs TEMPERATURE OUTPUTS SOURCE RESISTANCE vs TEMPERATURE 25 RSRC - Outputs Source Resistance - W RSRC - Outputs Source Resistance - W 25 RSRC_OUTF RSRC_OUTC 23 RSRC_OUTA 21 19 17 15 RSRC_OUTE RSRC_OUTD 23 RSRC_OUTB 21 19 17 15 -40 25 125 -40 25 TJ - Temperature - °C 125 TJ - Temperature - °C Figure 43. Figure 44.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DCM THRESHOLD vs TEMPERATURE 0.405 DCM - DCM Threshold - V 0.400 0.395 0.390 0.385 0.380 0.380 0.375 -40 25 125 TJ - Temperature - °C Figure 47.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Major waveforms of the phase-shifted converter during nominal operation mode are shown in Figure 48. Upper six waveforms in the Figure 48 show the output drive signals of the controller. At nominal mode, the outputs OUTE and OUTF overlap during the part of the switching cycle when the both rectifier MOSFETs are conducting and the windings of power transformer are shorted.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output inductor at the light load, during parallel operation and at some transient conditions. Such reverse current results in circulating of some extra energy between the input voltage source and the load and, therefore, causes increased losses and reduces efficiency. Another negative effect of such reverse current is the loss of ZVS condition.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com Experimental Results Example The following experimental results are based on 660-W output power prototype of phase shifted full-bridge DC/DC converter. The input voltage is 300 V to 400 V and the output is 12 V, 55 A. The primary MOSFETs are SPA11N60CFD and the synchronous rectifier MOSFETs are FDP047AN08A0, two in parallel. The measured efficiency of the prototype is shown in Figure 51.
UCC28950 SLUSA16B – MARCH 2010 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Original (March 2010) to Revision A Page • Changed UCC28950 Typical Application Diagram ............................................................................................................... 1 • Changed Converter switching frequency from 1400 kHz to 1000 kHz ................................................................................. 3 • Changed Functional Block Diagram .....................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC28950PWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28950PWR TSSOP PW 24 2000 367.0 367.0 38.
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