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UCC2897A

SLUS829D -- AUGUST 2008 -- REVISED JULY 2009

ADVANCED CURRENT-MODE

ACTIVE CLAMP PWM CONTROLLER

www.ti.com

FEATURES

D Low Output Jitter

D “Soft Stop” shut down of MAIN and AUX

D 110-V Input Startup Function

D Ideal for Active Clamp/Reset Forward,

Flyback and Synchronous Rectifier Uses

D Provides Complementary Auxiliary Driver

with Programmable Deadtime (Turn-On

Delay) between AUX and MAIN Switches

D Peak Current-Mode Control with 0.5-V

Cycle-by-Cycle Current Limiting

D TrueDrivet 2-A Sink, 2-A Source Outputs

D Trimmed Internal Bandgap Reference for

Accurate Line UV and Line OV Threshold

D Programmable Slope Compensation

D High-Performance 1.0-MHz Synchronizable

Oscillator with Internal Timing Capacitor

D Precise Programmable Maximum Duty Cycle

D PB-Free Lead Finish Package

APPLICATIONS

D High-Efficiency DC/DC Power Supplies

D Server Power, 48-V Telecom, Datacom, and

42-V Automotive Applications

DESCRIPTION

The UCC2897A PWM controller simplifies

implementation of the various active clamp/reset

and synchronous rectifier switching power

topologies.

The UCC2897A is a peak current-mode, fixed-

frequency, high-performance pulse width modulator .

It includes the logic and the drive capability for the

P-channel auxiliary switch along with a simple

method of programming the critical delays for

proper active clamp operation.

Features include an internal programmable slope

compensation circuit, precise D

MAX

limit, and a

synchronizable oscillator with an internal timing

capacitor. An accurate line monitoring function

also programs the converter’s ON and OFF

transitions with regard to the bulk input voltage,

VIN.

The UCC2897A adds a second level hiccup mode

current sense threshold, bi-directional

synchronization and input overvoltage protection

functionalities. The UCC2897A is offered in 20-pin

TSSOP (PW) and 20-pin QFN (RGP) package.

TYPICAL APPLICATION DIAGRAM

BIAS

OUT

AUX

RDEL

RON

ROFF

SYNC

LINEUV

OUT

AUX

PGND

6VREF

DEL

LINEOV

UCC2897A

8GND

9CS

10 RSLOPE

17VDD

VREF

OFF

SLOPE

SECONDARY

SIDE E/A

LOAD

DRIVE

BIAS

WINDING

+VIN

VIN

PVDD

SS/SD12

These devices have limited built -in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCTION DATA information is curre nt as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (43 pages)

PAGE 1
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ADVANCED CURRENT-MODE ACTIVE CLAMP PWM CONTROLLER FEATURES D Low Output Jitter D “Soft Stop” shut down of MAIN and AUX D 110-V Input Startup Function D Ideal for Active Clamp/Reset Forward, DESCRIPTION The UCC2897A PWM controller simplifies implementation of the various active clamp/reset and synchronous rectifier switching power topologies.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Line input voltage, VIN Supply voltage, VDD (IDD < 10 mA) Analog inputs FB, CS, SYNC, LINEOV, LINEUV Output source current (peak), IO_SOURCE Output sink current (peak), IO_SINK 120 V 16.5 V --0.3 to (VREF + 0.3) V 2.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ORDERING INFORMATION PART NUMBERS{ TA APPLICATION AUX OUTPUT POLARITY CYCLE-BYCYCLE CS THRESHOLD HICCUP MODE CS THRESHOLD 110-V HV JFET START-UP CIRCUIT TSSOP--20 (PW)} QFN--20 (RGP)} --40°C 40°C to 125°C DC/DC P Channel P-Channel 05V 0.5 0 75 V 0.75 Yes UCC2897APW UCC2897ARGP The PW package is available taped and reeled. Add R suffix to device type (e.g. UCC2897APWR) to order quantities of 2,000 devices per reel.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-μF capacitor from VDD to GND, 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-μF capacitor from VDD to GND, 0.01-μF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, --40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYNCHRONIZATION SYNC input high voltage 3.0 V SYNC input low voltage 1.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL BLOCK DIAGRAM VIN N/C 1 2 2.5V VREF IRDEL RDEL VREF 3 2.5V 0.05 × IRDEL CLOCK Start ICHG RON LineOV LineUV 1--DMAX 2.5V N/C 19 LINEOV 18 LINEUV 17 VDD 1.27 V End 4 20 0.05 × IRDEL 1.27 V IDSCHG 13V / 8V VDD CT ROFF 5 OUT SYNC VDD VREF PWM OFF 16 PVDD IRDEL VREF SYNC 6 REF GEN Q R Q Turn--on Delay IRDEL VREF 13 PGND 12 SS/SD 0.43 × ICHG 1--DMAX R 4×R VDD VREF LineUV LineOV RSLOPE 10 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 TERMINAL FUNCTIONS TERMINAL UCC2897A TSSOP--20 (PW) UCC2897A QFN--20 (RGP) I/O AUX 14 11 O This output drives the auxiliary clamp MOSFET which is turned on when the main PWM switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-on current and 2-A sink turn-off current. CS 9 6 I This pin is used to sense the peak current utilized for current mode control and for current limiting functions.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS RDEL This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND sets the turn-on delay for both gate drive signals of the UCC2987A controller. The delay time is identical for both switching transitions, between OUT is turning off and AUX is turning on as well as when AUX is turning off and OUT is turning on. The delay time is defined as: t DEL1 = t DEL2 = 11.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VREF The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a high quality ceramic bypass capacitor (CVREF) to GND for noise filtering and to provide compensation to the regulator circuitry. The recommended CVREF value is 0.22-μF and X7R capacitors are recommended. The minimum bypass capacitor value is 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) CS This is a direct input to the PWM and current limit comparators of the UCC2897A controller. The CS pin should never be connected directly across the current sense resistor (RCS) of the power converter.
PAGE 11
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) SS/SD A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the power converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by the RON resistor connected to pin 2. The soft-start current is defined as: I SS = 0.43 × I RON = 0.43 × V REF × 1 2 R ON (6) This DC current charges CSS from 0 V to approximately 5 V.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VDD The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate filtering.
PAGE 13
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VIN The UCC2897A controller is equipped with a high voltage, N-channel JFET start up device to initiate operation from the input power source of the converter in applications where the input voltage does not exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected directly to the positive terminal of the input power source.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION JFET Control and UVLO The UCC2897A controller includes a high voltage JFET start up transistor. The steady state power consumption of the of the control circuit which also includes the gate drive power loss of the two power switches of an active clamp converter exceeds the current and thermal capabilities of the device.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION As the controller starts operation it draws its bias power from the CBIAS capacitor until the bootstrap winding takes over (refering to Figure 10 and Figure 11). During this time VDD voltage is falling rapidly as the JFET is already off but the bootstrap voltage is still not sufficient to power the control circuits.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOFF VIN V CLAMP, MAX VCLAMP VSS TSW OUT AUX Figure 3. Line Undervoltage Shutdown Waveforms, P--Channel To eliminate this potential hazard the UCC2897A controller safely discharge the clamp capacitor during power down. The OUT and the AUX output continues switching while the soft-start capacitor CSS is being slowly discharged.
PAGE 17
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOVP VOVH VIN VSS OUT AUX Figure 4. Line Overvoltage Sequence, P--Channel Pulse Skipping During output load current transients or light load conditions most PWM controllers needs to be able to skip some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily to the main switch, this would apply the clamp voltage across the transformer continuously.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION Synchronization The UCC2897A has a bi-directional synchronization pin. In the stand-alone operation the SYNC pin is driven by the internal oscillator of the UCC2897A which provides an approximately 5-V amplitude square wave output. This signal can be used to synchronize other PWM controllers or circuits needing a constant frequency time base.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 FUNCTIONAL DESCRIPTION When a wider than 1 − D MAX × T SYNC pulse is connected to the SYNC input, the oscillator is not able to maintain the maximum duty cycle, originally set by the timing resistor ratio (RON, ROFF). Furthermore, the timing capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE The UCC2897A family offers a highly integrated feature set and excellent accuracy to control an active clamp forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design procedure. Refer to Figure 7 setup diagrams for component names.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Note, that tSS defines a time interval to reach the maximum current capability of the converter and not the time required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme does not allow accurate control over the ramp up time of the output voltage.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Step 5. Input Voltage Monitoring The input voltage monitoring functions is governed by the following two expressions of the voltage at the LINEUV pin: V LINEUV = V ON × R IN2 at turn on, and R IN1 + R IN2 V LINEUV = V OFF × R IN2 R × R IN2 + I HYST × IN1 at turn off. R IN1 + R IN2 R IN1 + R IN2 (19) (20) Since VON and VOFF are given by the power supply specification, VLINEUV equals the 1.
PAGE 23
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE In the UCC2897A controllers, slope compensation is implemented by sourcing a linearly increasing current at the CS pin. When this current passes through the current sense filter resistor (RF), it is converted to a slope compensation ramp which can be characterized by its dV S∕dt.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION Gate Drive Connection The low side P-channel gate drive circuit involves a level shifter using a capacitor and a diode which ensures that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter. Detailed analysis and design examples of these and many similar gate drive solutions are given in reference [6]. +VIN CCLAMP QAUX QMAIN AUX P Figure 9.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across the bootstrap winding equals the input voltage times the turns ratio.
PAGE 26
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases, the bias voltages are proportional to the output voltage.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 + + ADDITIONAL APPLICATION INFORMATION www.ti.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 TYPICAL CHARACTERISTICS UVLO VOLTAGE THRESHOLDS vs JUNCTION TEMPERATURE 12 2.5 UVLO On 2.0 IDD -- Supply Current -- mA VUVLO -- UVLO Voltage Thresholds -- V 14 QUIESCENT CURRENT vs SUPPLY VOLTAGE 10 8 UVLO Off 6 UVLO Hysteresis 4 1.5 1.0 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 TYPICAL CHARACTERISTICS VTH -- Line Thresholds -- V 1.28 1.26 1.24 1.22 1.20 --50 --25 0 25 50 75 TJ -- Junction Temperature -- °C 100 15 Softstart Discharge Current 10 5 0 --5 --10 --15 --20 --50 125 Softstart Charge Current --25 0 25 50 75 100 125 TJ -- Junction Temperature -- °C Figure 17 Figure 16 SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 10 M 0.60 SWITCHING FREQUENCY vs PROGRAMMING RESISTANCE 0.58 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 74 275 RON = ROFF = 75 kΩ 265 260 255 250 245 240 235 72 71 70 69 68 67 230 225 --50 RON = ROFF = 75 kΩ 73 DMAX -- Maximum Duty Cycle -- % fSW -- Switching Frequency -- kHz 270 MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE --25 0 25 50 75 TJ -- Junction Temperature -- °C 100 66 --50 125 --25 0 25 0.8 Hiccup Mode 0.6 Cycle-by-Cycle Current Limit 0.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 TYPICAL CHARACTERISTICS DELAY TIME vs DELAY RESISTANCE OUT AND AUX RISE AND FALL TIME vs JUNCTION TEMPERATURE 25 800 CLOAD = 2 nF 700 t DEL1 600 15 tDEL -- Delay Time -- ns tR/tF -- Rise and Fall Times -- ns Rise Time 20 Fall Time 10 t DEL2 500 400 300 200 5 100 0 --50 0 --25 0 25 50 75 100 TJ -- Junction Temperature -- °C 125 0 10 20 40 50 60 70 100 125 RDEL -- Delay Resistance -- kΩ Figure 25 Figure 24 DELAY TIME vs JUNC
PAGE 32
UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 5.3 REFERENCE VOLTAGE vs TEMPERATURE No Load 10 mA Load VREF -- Reference Voltage -- V 5.2 5.1 5.0 4.9 4.8 4.7 --50 --25 0 25 50 75 100 125 TJ -- Junction Temperature -- °C Figure 28 32 www.ti.
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UCC2897A SLUS829D -- AUGUST 2008 -- REVISED JULY 2009 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°--8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC2897APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 UCC2897ARGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC2897ARGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2897APWR TSSOP PW 20 2000 367.0 367.0 38.0 UCC2897ARGPR QFN RGP 20 3000 367.0 367.0 35.0 UCC2897ARGPT QFN RGP 20 250 210.0 185.0 35.
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