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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007

 

 

www.ti.com

FEATURES

High Accuracy, Better Than 1% CurrentShare

Error at Full Load

D High-Side or Low-Side (GND Reference)

Current-Sense Capability

D Ultra-Low Offset Current Sense Amplifier

D Single Wire Load Share Bus

D Full Scale Adjustability

D Intel



SSI LoadShare Specification Compliant

D Disconnect from Load Share Bus at Stand-By

D Load Share Bus Protection Against Shorts to

GND or to the Supply Rail

D 8-Pin MSOP Package Minimizes Space

D Lead-Free Assembly

SYSTEM CONFIGURATIONS

Modules With Remote Sense Capability

D Modules With Adjust Input

D Modules With Both Remote Sense and Adjust

Input

D In Conjunction With the Internal Feedback E/A

of OEM Power Supply Units

DESCRIPTION

The UCC39002 is an advanced, high performance and

low cost loadshare controller that provides all

necessary functions to parallel multiple independent

power supplies or dc-to-dc modules. Targeted for high

reliability applications in server, workstation, telecom

and other distributed power systems, the controller is

suitable for N+1 redundant systems or high current

applications where off-the-shelf power supplies need to

be paralleled.

The BiCMOS UCC39002 is based on the automatic

master/slave architecture of the UC3902 and UC3907

load share controllers. It provides better than 1%

current share error between modules at full load by

using a very low offset post-package-trimmed

current-sense amplifier and a high-gain negative

feedback loop. And with the amplifier’s common mode

range of 0-V to the supply rail, the current sense

resistor, R

SHUNT

, can be placed in either the GND return

path or in the positive output rail of the power supply.

CS+

VDD

CSO

EAO

ADJ

UCC39002

V+V+

S+

V−

S−

LOAD

POWER

SUPPLY

WITH

REMOTE

SENSE

TYPICAL LOW-SIDE CURRENT SENSING APPLICATION

LS BUS

SYSTEM+

SYSTEM+−

SHUNT

ADJ

CS−

5GND

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Summary of content (28 pages)

PAGE 1
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FEATURES D High Accuracy, Better Than 1% CurrentShare D D D D D D D D D DESCRIPTION The UCC39002 is an advanced, high performance and low cost loadshare controller that provides all necessary functions to parallel multiple independent power supplies or dc-to-dc modules.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESCRIPTION (continued) The functionality of the UCC29002/1 differs slightly compared to the UCC39002. The UCC39002 will force the maximum adjustment range at start up to quickly engage load sharing; the UCC29002/1 ADJ amplifier will operate in a linear mode during start up, resulting in a more gradual load sharing at turn on.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 electrical characteristics VDD = 12 V, 0°C < TA < 70°C for the UCC39002, −40°C < TA < 105°C for the UCC29002 and UCC29002/1, TA = TJ (unless otherwise noted) general PARAMETER TEST CONDITIONS Supply current LS with no load, VDD clamp voltage IDD = 6 mA MIN TYP ADJ = 5 V MAX UNITS 2.5 3.5 13.50 14.25 15.00 mA V UNITS undervoltage lockout MIN TYP MAX Start-up voltage(1) PARAMETER TEST CONDITIONS 4.175 4.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 electrical characteristics VDD = 12 V, 0°C < TA < 70°C for the UCC39002, −40°C < TA < 105°C for the UCC29002 and UCC29002/1, TA = TJ (unless otherwise noted) (continued) error amplifier PARAMETER TEST CONDITIONS VOH gM High-level output voltage IOH MIN TYP 3.50 Transconductance IOUT_EAO = 0 mA IEAO = ± 50 µA High-level output current VLS − VCSO = 0.4 V,REAO = 2.2 kΩ 0.70 MAX 3.65 3.80 14 0.85 UNITS V mS 1.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 typical high-side current sensing application RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 S− V− RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 LOAD S− V− RSHUNT V+ RADJ S+ UCC39002 POWER SUPPLY WITH REMOTE SENSE 1 CS− CSO 8 2 CS+ LS 7 3 VDD EAO 6 4 GND ADJ 5 S− V− www.ti.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 functional block diagram Current Sense Amp CS− 1 8 CSO Disconnect Switch + + CS+ 2 VBIAS VDD Enable and Bias OK 7 LS Load Share Bus Receiver + 3 100 kΩ Error Amp + gM 13.5 V to 15 V GND Load Share Bus Driver 4 Fault Protection 6 EAO 3V Start Up and Adjust Logic 3V 5 ADJ Adjust Amp + 500 Ω UDG−02086 6 www.ti.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION differential current sense amplifier (CS+, CS−, CSO) The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value current sense resistor. Since the amplifier is fully uncommitted, the current sense gain is user programmable.
PAGE 8
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION error amplifier (EAO) As pictured in the block diagram, the UCC39002 employs a transconductance also called gM type error amplifier. The gM amplifier was chosen because it requires only one pin, the output to be accessible for compensation. The purpose of the error amplifier is to compare the average, per module current level to the output current of the respective module controlled by the UCC39002.
PAGE 9
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION enable function (CS+, CS−) The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During normal operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of the enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately 0.
PAGE 10
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION start up and adjust logic The start up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states.
PAGE 11
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 FUNCTIONAL DESCRIPTION The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable function with a 4.375-V threshold. While VDD < 4.375 V the load share control functions are disabled. While this might be inconvenient for some low voltage applications it is necessary to ensure high accuracy.
PAGE 12
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modules for load sharing.
PAGE 13
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE measuring the modules’ loop Using the configuration in Figure 6, measure the unity gain crossover frequency of the power modules to be paralleled. A typical resultant bode plot is shown in Figure 7. + VIN + + VOUT DC−DC Module Load 50 Ω + SENSE XFRMR Source Out Channel A Channel B Network Analyzer UDG−02079 Figure 6.
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SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE the shunt resistor Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop should be much less than the voltage adjustment range of the module: I OUT(max) R SHUNT tt D V ADJ(max) (3) Other limitations for the sense resistor are the desired minimum power dissipation and available component ratings.
PAGE 15
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE determining RADJUST The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across RADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at approximately 1 V above the voltage at the EAO pin.
PAGE 16
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE error amplifier compensation The total load-share loop unity-gain crossover frequency, fCO, should be set at least one decade below the measured crossover frequency of the paralleled modules previously measured, fCO(module). (See Figure 7) Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor, REAO, and capacitor, CEAO, between EAO and GND.
PAGE 17
SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007 DESIGN PROCEDURE references For further details, refer to the following document: D Reference Design, 48-VIN , 12-VOUT Loadshare System Using UCC39002 with Three DC/DC PH-100S4 Modules”, Texas Instruments Literature No. SLUA270 For a more complete description of general load sharing toics, refer to the following documents.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC29002DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC29002DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC29002DR/1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC29002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC29002DR SOIC D 8 2500 367.0 367.0 35.0 UCC29002DR/1 SOIC D 8 2500 367.0 367.0 35.0 UCC39002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC39002DR SOIC D 8 2500 367.0 367.0 35.
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