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 

   



SLUS431A – MAY 2000 – REVISED DECEMBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 Operates with Secondary–Side PWM

Control

 Isolated PWM Command through a Pulse

Transformer

 Initial Free-Running Soft-Startup with

Duty-Cycle Clamping

 Up to 400-kHz Synchronizable Switching

Frequency

 High-Current FET Drive (1.5-A Sink, 0.75-A

Source)

 Multi-Mode Overcurrent Protection with

Restart, Latching, or Cycle-by-Cycle

Current Limiting

 Programmable Volt-Second Clamp for

Transformer Reset

 Undervoltage Lockout with 2-V Hysteresis

 Low-Current Startup with Optional

Disconnect

 Programmable Overvoltage and

Undervoltage Protection

 8–pin Version Also Available (UCC3960)

typical application diagram

UDG–99039

UV/OV

STOP

FEED

BACK

SOFT START

FREQ

SET

CSD

PGND

OUT

VDD

START

AGND

OVS

UVS

OPTIONAL

DEPLETION

MODE

SWITCH

FAULT LATCH DELAY

VOLT

SEC

CLAMP

UCC3961

–

REF

        

         

       

   

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
. / SLUS431A – MAY 2000 – REVISED DECEMBER 2000 Operates with Secondary–Side PWM Multi-Mode Overcurrent Protection with Control Isolated PWM Command through a Pulse Transformer Initial Free-Running Soft-Startup with Duty-Cycle Clamping Up to 400-kHz Synchronizable Switching Frequency High-Current FET Drive (1.5-A Sink, 0.
PAGE 2
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 description The UCC3961 advanced primary-side startup controller is a unique solution that provides all the primary-side functions required for a single-ended, isolated, switch-mode power converter incorporating secondary-side PWM control. It is usable with a wide range of secondary control circuits and is especially well suited for systems where sophisticated handling of overload conditions is required.
PAGE 3
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡ Input voltage, VI(VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V Input current, II(VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 electrical characteristics VDD = 12 V, RT = 53.3 kΩ, CVDD = 1 µF, CREF = 0.1 µF, CSS = 0.01 µF, ROUT = 4 Ω, COUT = 1 nF and TA = TJ (unless otherwise stated) supply section (VDD) PARAMETER Clamp voltage TEST CONDITIONS MIN TYP MAX UNITS 16 17.5 19 V Operating current IVDD = 10 mA No load, COUT = 0 1.8 2.3 2.
PAGE 5
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 electrical characteristics VDD = 12 V, RT = 53.3 kΩ, CVDD = 1 µF, CREF = 0.1 µF, CSS = 0.01 µF, ROUT = 4 Ω, COUT = 1 nF and TA = TJ (unless otherwise stated) (continued) current sense section (CS) PARAMETER Threshold Input bias TEST CONDITIONS MIN TYP MAX UNITS Pulse-by-pulse 0.9 1 1.1 V Immediate 1.3 1.4 1.5 V 0.2 µA 60 100 140 ns 600 800 1000 Ω MAX UNITS CS = 1.
PAGE 6
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 Terminal Functions TERMINAL NAME NO. AGND 7 CS 9 I/O DESCRIPTION This pin is the reference point for grounding all analog functions and must be kept as clean as possible from all switching noise. It should be connected to PGND in only one location as close to the IC as practical.
PAGE 7
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 timing resistor (RT) A resistor from this pin to AGND establishes a current, I SET 2V RT that is mirrored internally for several functions. It establishes the free-running startup switching frequency with an internal capacitor according to the relationship, fs 8.
PAGE 8
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 pin descriptions (continued) UNDER–VOLTAGE UVS VDD REG 14 12 V + 13 START 4V SOFT START OVER–VOLTAGE OVS 1 VS 8 4V VOLT–SEC LMT 1V UVLO S/D LATCH Q R Q S 10 / 8 V 12 VDD 6 VREF 11 OUT REF 5.0 V GEN 17 V 1V PWM LATCH STOP + FB 4 1V 5V ISS SS START Q S Q SD S/S PWM LO HI 1.0V 9 CS 2 SD ISD 5 HI SYNC LO MAX D/C OSCILL CT 10 PGND 5V 2 ISS AGND 1.
PAGE 9
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 DETAILED DESCRIPTION soft start The soft-start section contains all the circuitry required to produce a user programmable slowly increasing PWM duty cycle, starting from 0% to a maximum of 72%. The soft-start cycle is triggered either by the initial primary-side startup procedure or after any one of three user-programmable fault conditions and one fixed-fault condition.
PAGE 10
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 DETAILED DESCRIPTION undervoltage lockout The undervoltage lockout (UVLO) circuit enables normal operation after VDD exceeds the 10.0-V turnon threshold and permits operation until VDD falls below the 8-V turnoff threshold. While activated, the UVLO circuit holds the PWM gate driver output (OUT) and the internal-reference buffer amplifier output REF low.
PAGE 11
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 DETAILED DESCRIPTION start regulator and VDD clamp To facilitate the primary-side startup, a VDD = 12V voltage regulator may be implemented by using an external depletion-mode FET. The gate of this device is then connected to the START pin, the source terminal is attached to the VDD pin, and the drain is tied to the HV primary-side power input that is derived from the rectified line voltage.
PAGE 12
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 APPLICATION INFORMATION The evaluation circuit of UCC3961 as the primary-side startup circuit and UCC38C45 as the secondary-side controller is shown in Figure 2. UP4–101 MUR610 VIN 470µF 470µF MUR110 10 Ω IRF530 1 kΩ 4.7 kΩ 22 kΩ 27 kΩ 0.5Ω 36 kΩ UCC38C45 12 V 8 VREF 1 nF 3.9 kΩ 0.1µF 36 kΩ COMP 1 VDD FB 2 6 OUT CS 3 5 GND RT 4 7 6.2 kΩ 0.1µF OUT 10 kΩ 4.7µF 6.
PAGE 13
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 APPLICATION INFORMATION pulse edge transmission circuit The UCC3961 uses a pulse-edge-transmission (PET) circuit to transmit isolated gate-pulse information from the secondary-side controller. It is important for the PET circuit to have proper frequency response and adequately high damping (low Q-factor) in order to prevent excessive overshoot. The circuit is shown in Figure 3.
PAGE 14
SLUS431A – MAY 2000 – REVISED DECEMBER 2000 PARAMETER MEASUREMENT INFORMATION OPERATING WAVEFORMS DURING OVERLOAD NORMAL OPERATING WAVEFORMS Figure 5 Figure 4 OPERATING WAVEFORMS DURING NO LOAD Figure 6 ADDITIONAL REFERENCES 1. Dennis, Mark and Michael Madigan, 50-W Forward Converter with Synchronous Rectification and Secondary-Side Control, SEM–1300, Topic 4, Texas Instruments Literature Number SLUP002.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC3961DTR Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC3961DTR SOIC D 14 2500 367.0 367.0 38.
PAGE 19
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