Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - PFC 8 mA TSSOP 14

BIASSNS

12 BIASCTRL

LINESNS

VDD

TST

PFCDRV

3CS

5CS

2VBULK

7 6 14 8

NC REFIN VSS FAULT

UCC29910APW

BIAS

SUPPLY

DRIVER

EMC

FILTER

HS BULK

SENSE

VAC

BULK

UCC29910A

www.ti.com

SLUSAK8A – MAY 2011– REVISED JUNE 2011

Buck PFC Controller

Check for Samples: UCC29910A

FEATURES

DESCRIPTION

The UCC29910A Buck Power Factor Correction

• Buck Power Factor Correction for High

(PFC) controller provides a relatively flat

Efficiency Across Line

high-efficiency performance across universal line for

• Low Off-Line Startup Current, With SmartStart

designers requiring a high power factor (>0.9) and

Algorithm for Fast Startup With Soft-Start

wishing to meet the requirements of IEC 61000-3-2.

• Compatible With Resistive or Pass Transistor

Based on a buck topology, inherent inrush current

Fed Startup from the AC Line

limiting eliminates the need for additional

• Low Power SmartBurst Mode for Standby and

components. With a typical bus voltage of 84 V, the

Light-Load Conditions

topology is ideally suited for use with low voltage

stress downstream regulation/isolation power trains,

• Current Sense Inputs for PFC control and

such as half-bridge stages controlled by the

Overload Protection

UCC29900, (Texas Instruments Literature Number,

• Line Sense UVLO

SLUS923). This combination offers low

• Sense and Drive Control for External Startup

common-mode noise generation allowing reduced

Depletion Mode FET

filtering and exceptionally high conversion efficiency.

• Latching Fault Input Pin

The UCC29910A incorporates AC line UVLO and

controlled soft start for fast start-up. Enhanced

APPLICATIONS

light-load efficiency is achieved through advanced

• High Efficiency AC-DC Adapters

management algorithms for best-in-class no-load and

• Low Profile and High Density Adapters

light-load performance.

SIMPLIFIED APPLICATION DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Buck PFC Controller Check for Samples: UCC29910A FEATURES DESCRIPTION • The UCC29910A Buck Power Factor Correction (PFC) controller provides a relatively flat high-efficiency performance across universal line for designers requiring a high power factor (>0.9) and wishing to meet the requirements of IEC 61000-3-2. Based on a buck topology, inherent inrush current limiting eliminates the need for additional components.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range, all the voltages refer to the VSS pin (unless otherwise noted) MIN TA Operating free air temperature MAX UNIT −40 105 °C 3.0 3.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com DEVICE INFORMATION UCC29910A 14- Pin TSSOP (PW) VDD 1 14 VSS VBULK 2 13 PFCDRV CS 3 12 BIASCTRL LINESNS 4 11 NC CS 5 10 TST REFIN 6 9 BIASSNS NC 7 8 FAULT TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VDD 1 - Provides power to the device; should be decoupled with ceramic capacitor (1 µF), connected directly across pins 1-14. VBULK 2 I Voltage sensing of the bulk capacitor.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Detailed Pin Description Pin 1 – VDD: This pin supplies power to the device. A minimum supply voltage level of 3.0 V and maximum of 3.6 V is recommended. Pin 2 – VBULK: The output voltage level, VBULK is sensed on this pin. The HV bulk sensing network should be scaled so that the desired output voltage produces VNM at this pin. The Thevenin impedance at this pin should be below 20 kΩ, with appropriate capacitance provided for noise filtering.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Pin 8 – FAULT: This pin when pulled low causes PFCDRV and BIASCTRL to go low, typically within 10 us. After a 100 us delay the FAULT input is sampled again. If the FAULT has cleared high, the UCC29910A goes into SmartStart mode. If the FAULT input is still low the device enters a latched shutdown state.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION The UCC29910A controls a Buck PFC stage and is particularly suited to AC/DC applications in the power range from 65 W to 130 W. A fully characterised reference design using the UCC29910A PFC controller and the UCC29900 Integral Cycle Controller is available on request. The design is for a 90 W PSU intended for laptop adapter applications.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Control system The UCC29910A uses an average current mode control loop to regulate the output voltage, this eliminates the need for slope compensation. The two inputs to this control loop are the voltages at the VBULK and CS (Current Sense) pins. Voltage Loop – PI Error Amp The output of the PI (Proportional Integral) Error Amplifier is proportional to the difference between the voltages at the VBULK pin and the REFIN pins.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com BULK OV Clamp The low bandwidth of the normal control loop prevents it from controlling an increase in VBULK due for example, to a large step reduction in the load on the VBULK output. This clamp activates within 120 µs if the voltage at the VBULK pin exceeds 107% of VNM. When activated, it blanks the gate control logic output and the PFCDRV pin is held low. This clamp is non-latching so it releases once VBULK falls below trip level, i.e.
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UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Buck PFC Power Stage The PFC stage converts the incoming rectified line voltage to a DC voltage on the output capacitors, power transfer happening during the times when the line voltage is greater than the output voltage. The resulting conduction angle is a function of both the incoming line and output voltages. In the reference design mentioned above, the output voltage is set to 84 VDC.
PAGE 11
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com The buck converter operates off a rectified sinusoid and there are periodic dead times when the input voltage is lower than the output. During these times no power can be transferred to the output and the input current is nominally zero. Figure 2 shows the line current, IAC, falling to zero when VAC is less than VBULK.
PAGE 12
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Start-Up With External FET Conventional start-up schemes utilising either resistive or enhancement mode MOSFET feeds incur line dependant static power losses. To avoid these power losses and to obtain an optimum turn-on time an external depletion mode FET may be used Figure 5 and Figure 6. The VHV node is connected to the rectified incoming line. Q12 is a depletion mode FET which will start charging C45 as soon as line power is connected.
PAGE 13
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Figure 6.
PAGE 14
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com SmartStart, VBULK Ramp-Up Once VCCA has reached 12 V and Q12 has been turned off, and VLINESNS > VBH, the PFCDRV output of U1 becomes active and begins driving the main power MOSFET. The SmartStart algorithm increases VBULK, the voltage across C2 and C21, as rapidly as possible. This is done by transferring the maximum amount of energy possible during each pulse set.
PAGE 15
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Normal Mode Operation In normal mode, the VBULK pin is controlled at VNM. Due to the slow voltage loop, and low gain at 100/120 Hz, the voltage loop PI error amp output will be essentially a fixed demand. If the power stage stays in Discontinuous Conduction Mode (DCM) throughout the half-cycle, then peak current will be proportional to (VHV-VBULK) over the half cycle and IAVG is approximately proportional to IPEAK.
PAGE 16
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com PFC Inductor Value The PFC inductor is designed for an inductance value that ensures DCM operation at high line (i.e. >160 VAC), right up to full-peak load. With an appropriate value of inductance, operation at low line should then result in CCM operation over most of the conduction angle at full load.
PAGE 17
UCC29910A SLUSAK8A – MAY 2011 – REVISED JUNE 2011 www.ti.com Bulk Capacitor Choice The value of bulk capacitance required is dictated by requirements on the allowable ripple voltage and hold-up time.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC29910APWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC29910APWR TSSOP PW 14 2000 367.0 367.0 35.
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