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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009

     

   

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FEATURES

D Programmable Slope Compensation

D Internal Soft-Start on the UCC38083/4

D Cycle-by-Cycle Current Limiting

D Low Start-Up Current of 120 µA and 1.5 mA

Typical Run Current

D Single External Component Oscillator

Programmable from 50 kHz to 1 MHz

D High-Current Totem-Pole Dual Output Stage

Drives Push-Pull Configuration with 1-A Sink

and 0.5-A Source Capability

D Current Sense Discharge Transistor to

Improve Dynamic Response

D Internally Trimmed Bandgap Reference

D Undervoltage Lockout with Hysteresis

APPLICATIONS

D High-Efficiency Switch-Mode Power Supplies

D Telecom dc-to-dc Converters

D Point-of-Load or Point-of-Use Power Modules

D Low-Cost Push-Pull and Half-Bridge

Applications

DESCRIPTION

The UCC38083/4/5/6 is a family of BiCMOS pulse width

modulation (PWM) controllers for dc-to-dc or off-line

fixed-frequency current-mode switching power

supplies. The dual output stages are configured for the

push-pull topology. Both outputs switch at half the

oscillator frequency using a toggle flip-flop. The dead

time between the two outputs is typically 110 ns, limiting

each output’s duty cycle to less than 50%.

The new UCC3808x family is based on the UCC3808A

architecture. The major differences include the addition

of a programmable slope compensation ramp to the CS

signal and the removal of the error amplifier. The current

flowing out of the ISET pin through an external resistor

is monitored internally to set the magnitude of the slope

compensation function. This device also includes an

internal discharge transistor from the CS pin to ground,

which is activated at each clock cycle after the pulse is

terminated. This discharges any filter capacitance on

the CS pin during each cycle and helps minimize filter

capacitor values and current sense delay.

The UCC38083 and the UCC38084 devices have a

typical soft-start interval time of 3.5 ms while the

UCC38085 and the UCC38086 has less than 100 µs for

applications where internal soft-start is not desired.

The UCC38083 and the UCC38085 devices have the

turn-on/off thresholds of 12.5 V / 8.3 V, while the

UCC38084 and the UCC38086 has the turn-on/off

thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin

TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)

packages.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

UDG−01080

BASIC APPLICATION

OUTA

OUTB

CTRL

ISET

GND

VDD

SET

POWER

TRANSFORMER

UCC3808x

FEEDBACK

OUT

Summary of content (26 pages)

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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 FEATURES APPLICATIONS D D D D D D D D D D D D D Programmable Slope Compensation Internal Soft-Start on the UCC38083/4 Cycle-by-Cycle Current Limiting Low Start-Up Current of 120 µA and 1.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 ORDERING INFORMATION THERMAL RESISTANCE TABLE PACKAGE θjc(°C/W) SOIC−8 (D) 42 PDIP−8 (P) 50 32(2) θja(°C/W) 84 to 160(1) 110(1) 232 to 257(2) NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 inch2 aluminum PC board. Test PWB was 0.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (IDD < 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Supply current, IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 electrical characteristics over recommended operating virtual junction temperature range, VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF, RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ (unless otherwise noted) current sense PARAMETER TEST CONDITIONS Gain See Note 3 Maximum input signal voltage CTRL
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 functional block diagram Soft Start and Fault Latch CTRL 1 S Iss Bias/UVLO VREF Q 0.5V Slope Circuit ISLOPE 8 R Vdd−1 VDD S CT + R Css ISET Q I SLOPE = 5 x I SET 2 CS Circuitry 0.75V PWM Comparator/Latch Output Driver 7 OUTA 80 kΩ S 60 kΩ 0.5V CS Q Q T R 0.3 V Q 3 6 OUTB Oscillator 1.5V 1.5V S Q I CT R RT 4 5 CT 0.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 detailed pin descriptions CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to maintain a usable range with the minimum VDD of 4.1 V.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 detailed pin descriptions (continued) OUTA and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current. The output stages switch at half the oscillator frequency, in a push-pull configuration.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 APPLICATION INFORMATION The following application circuit shows an isolated 12-VIN to 2.5 VOUT push-pull converter with scalable output power (20 W to 200 W). Note that the pinout shown is for SOIC-8 and PDIP-8 packages. typical application V O= 2.2 V TO 3.3 V ADJUSTABLE VIN = 12 V +/−20%V SR DRIVE 1 µF 8 VDD 4.7Ω 7 OUTA RT 4 UCC3808x 4.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 APPLICATION INFORMATION operational waveforms Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element VCS, to implement slope compensation. OUTA OUTB VRS ADDED RAMP VOLTAGE VCS, Pin 3 UDG−01085 Figure 3.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 layout considerations To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended. Use a local ground plane near the small signal pins (CTRL, ISET, CS and RT) of the IC for shielding. Connect the local ground plane to the GND pin with a single trace.
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www.ti.com VCC See Note 2 2OUT 1OUT REG_OUT 2IN 1IN GND REG_IN 3 1 4 2 Note 1. C28, R25, and D12 accelerate the control to the secondary side feedback at start-up and prevent output voltage overshoot. Note 2. Components used for the UCC38085 only. + 5 7 8 6 + + SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 APPLICATION INFORMATION Figure 5.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs TEMPERATURE OSCILLATOR FREQUENCY vs TIMING RESISTANCE 220 1200 215 T = 85°C VDD = 15 V 1000 RT = 165 kΩ″ RF= 1 kΩ CF = 220 kΩ RSET = 50 kΩ Frequency − kHz 800 Frequency − kHz 210 T = 25°C VDD = 10 V 600 400 205 200 195 190 200 T = 40°C VDD = 6 V 185 180 0 10 100 −50 1000 0 25 50 75 100 125 Temperature − °C RT −
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 TYPICAL CHARACTERISTICS DEAD TIME vs TIMING RESISTANCE OVER VDD DEAD TIME vs TEMPERATURE 200 160 180 160 VDD = 6 V* T = 85°C T = 25°C RT = 165 kΩ″ RF= 1 kΩ CF = 220 kΩ RSET = 50 kΩ 140 120 Dead Time − ns VDD = 10 V Dead Time − ns VDD = 6 V* 140 120 100 VDD = 14 V 80 60 VDD = 14 V T = −40°C 100 80 60 40 40 20 20 * UCCx8084/6, only 0 0 10 1000 100 −50 −25 0 25
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 TYPICAL CHARACTERISTICS RAMP HEIGHT vs RT RAMP HEIGHT vs TEMPERATURE 0.7 0.6 TA = 25°C RSET = 10 kΩ 0.6 0.5 (OC Clamped) VPK(cs) − V 0.4 VPK(cs) − V RSET = 10 kΩ 0.5 (OC Clamped) RSET = 18 kΩ 0.3 0.4 0.3 0.2 0.2 RSET = 50 kΩ RSET = 18 kΩ RSET = 50 kΩ 0.1 0.1 RSET = 100 kΩ RSET = 100 kΩ 0 0.
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SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009 TYPICAL CHARACTERISTICS CS TO OUTX DELAY TIME vs TEMPERATURE 150 140 CS Prop Delay − ns 130 120 110 100 90 80 70 60 50 −50 −25 0 25 50 75 100 125 Temperature − °C Figure 18 RELATED PRODUCTS UCC3808, 8-Pin Low Power Current Mode Push-Pull PWM, (SLUS168) UCC3808A, 8-Pin Low-Power Current-Mode Push-Pull PWM, (SLUS456) UCC3806, Low Power, Dual Output, Current Mode PWM Controller
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC28083DR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC28084DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC28084PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC28085DR SOIC D 8 2500 330.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28083DR SOIC D 8 2500 340.5 338.1 20.6 UCC28084DR SOIC D 8 2500 340.5 338.1 20.6 UCC28084PWR TSSOP PW 8 2000 367.0 367.0 35.0 UCC28085DR SOIC D 8 2500 340.5 338.1 20.6 UCC28086DR SOIC D 8 2500 340.5 338.1 20.6 UCC28086PWR TSSOP PW 8 2000 367.0 367.0 35.0 UCC38083DR SOIC D 8 2500 340.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.