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   

   

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

 

 

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FEATURES

Combines PFC and Downstream Converter

Controls

D Controls Boost Preregulator to Near-Unity

Power Factor

D Accurate Power Limiting

D Improved Feedforward Line Regulation

D Peak Current-Mode Control in Second Stage

D Programmable Oscillator

D Leading-Edge/Trailing-Edge Modulation for

Reduced Output Ripple

D Low Start-up Supply Current

D Synchronized Second Stage Start-Up, with

Programmable Soft-start

D Programmable Second Stage Shutdown

DESCRIPTION

The UCC2850x family provides all of the control

functions necessary for an active power-factor-

corrected preregulator and a second-stage dc-to- dc

converter. The controller achieves near-unity power

factor by shaping the ac input line current waveform to

correspond to the ac input-line voltage using average

current-mode control. The dc-to-dc converter uses

peak current-mode control to perform the step-down

power conversion.

The PFC stage is leading-edge modulated while the

second stage is trailing-edge synchronized to allow for

minimum overlap between the boost and PWM

switches. This reduces ripple current in the bulk-output

capacitor.In order to operate with over three-to-one

range of input-line voltages, a line feedforward (V

) is

used to keep input power constant with varying input

voltage. Generation of V

is accomplished using I

conjunction with an external single-pole filter. This not

only reduces external parts count, but also avoids the

use of high-voltage components, offering a lower-cost

solution. The multiplier then divides the line current by

the square of V

The UCC2850x PFC section incorporates a low

offset-voltage amplifier with 7.5-V reference, a

highly-linear multiplier capable of a wide current range,

a high-bandwidth, low offset-current amplifier, with a

novel noise-attenuation configuration, PWM

comparator and latch, and a high-current output driver.

Additional PFC features include over-voltage

protection, zero-power detection to turn off the output

when VAOUT is below 0.33 V and peak current and

power limiting.

The dc-to-dc section relies on an error signal generated

on the secondary-side and processes it by performing

peak current mode control. The dc-to-dc section also

features current limiting, a controlled soft-start, preset

operating range with selectable options, and 50%

maximum duty cycle.

The UCC28500 and UCC28502 have a wide UVLO

threshold (16.5 V/10 V) for bootstrap bias supply

operation. The UCC28501 and UCC28503 are

designed with a narrow UVLO range (10.5 V/10 V) more

suitable for fixed bias operation. The UCC28500 and

UCC28501 have a narrow UVLO threshold for PWM

stage (to allow operation down to 75% of nominal bulk

voltage), while the UCC28502 and UCC38503 are

configured for a much wider operation range for the

PWM stage (down to 50% of bulk nominal voltage).

Available in 20-pin N and DW packages.

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Summary of content (35 pages)

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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 FEATURES D Combines PFC and Downstream Converter D D D D D D D D D Controls Controls Boost Preregulator to Near-Unity Power Factor Accurate Power Limiting Improved Feedforward Line Regulation Peak Current-Mode Control in Second Stage Programmable Oscillator Leading-Edge/Trailing-Edge Modulation for Reduced Output Ripple Low Start-up Supply Current Sy
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)†} Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Gate Drive Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted) supply current PARAMETER TEST CONDITIONS Supply current, off VCC turn-on threshold –300 mV Supply current, on VCC = 12 V (no load on GT1 or GT2) MIN TYP MAX UNITS 150 300 µA 4 6 mA undervoltage lockout PARAME
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted) voltage reference PARAMETER TEST CONDITIONS TA = 0°C to 70°C TA = –40°C to 85°C Input voltage Load regulation Line regulation IREF = −1 mA to −2 mA, VCC = 10.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted) PFC gate driver PARAMETER GT1 pull up resistance GT1 pull down resistance GT1 output rise time GT1 output fall time TEST CONDITIONS TYP CLOAD = 1 nF, VGT1 from 0.7 V to 9.0 V CLOAD = 1 nF, VGT1 from 9.0 V to 0.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 pin assignments CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse width modulator (PWM) to force the correct duty cycle. This output can swing close to GND, allowing the PWM to force zero duty cycle when necessary.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 pin assignments (continued) SS2: (soft-start for PWM) SS2 is at ground for either enable low or OVP/ENBL below the UVLO2 threshold conditions. When enabled, SS2 charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 block diagram VERR ISENSE2 7 8 SS2 VCC GND 9 6 13 7.5 V REFERENCE SECOND STAGE SOFT START OVP/ENBL + 4 1.9 V ILIMIT 4.5 V 1.5 V R R + 1.3 V PWM + 8.0 V + 3 0.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL CHARACTERISTICS MULTIPLIER OUTPUT CURRENT vs. VOLTAGE ERROR AMPLIFIER OUTPUT MULTIPLIER GAIN vs. VOLTAGE ERROR AMPLIFIER OUTPUT 1.5 300 1.3 IAC = 150 µ A IAC = 150 µ A 250 Multiplier Gain − K IMOUT - Multiplier Output Current − µA 350 200 IAC = 300 µ A 150 100 1.1 0.9 IAC = 300 µ A IAC = 500 µ A 0.7 50 IAC = 500 µ A 0.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 REFERENCE VOLTAGE vs. REFERENCE CURRENT REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 7.510 VREF − Reference Voltage − V VREF − Reference Voltage − V 7.60 7.55 7.50 7.45 7.505 7.500 7.495 7.490 7.40 9 10 11 12 13 14 5 10 15 20 IVREF − Reference Current − mA VCC − Supply Voltage − V Figure 5 10 0 Figure 6 www.ti.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION The UCC38500 series is designed to incorporate all the control functions required for a power factor correction circuit and a second stage dc-to-dc converter. The PFC function is implemented as a full-feature, average-current-mode controller integrated circuit. In addition, the input voltage feedforward function is implemented in a simplified manner.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION The UCC3850x is optimized to control a boost PFC stage operating in continuous conduction mode, followed by a dc-to-dc converter (typically a forward topology). The dc-to-dc converter is transformer isolated and therefore its error amplifier is located on the secondary side.
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AC−N AC−L www.ti.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION I. PFC Boost Power Stage LBOOST (L1 in Figure 9) The boost inductor value is determined by the following equations: P DI + ǒ0.25Ǔ OUT h1 h2 D+1* Ǹ2 , V IN (min) (1) Ǹ2 V IN (min) L BOOST + V BOOST , (2) V IN (min) Ǹ2 DI fS D (3) where ∆I, the inductor current ripple was set to approximately 25% of the peak inductor current.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION power switch selection (Q3 in Figure 9) As in any power supply design, tradeoffs between performance, cost and size are necessary. When selecting a power switch, it is useful to calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION peak current limit Resistor divider R14 and R29 along with current sense resistor R5, devise the peak-limit comparator of the UCC38500 and are used to protect the boost switch Q3 from excessive currents.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant and to providing input power limiting. Please refer to Texas instruments Application Note on Power Limiting with Sinusoidal Input TI Literature No.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION R MOUT + P LIMIT Ǹ2 R SENSE V IN (min) I MOUT(max) (18) current loop The UCC38500 current amplifier has the input from the multiplier applied to the inverting input. This change in architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier. It also adds a phase inversion into the control loop.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION C P C Rf Z RI − CAOUT + Figure 10. Current Loop Compensation voltage loop The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple at the input to the multiplier.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION In this example VOPK is equal to 4 V. Assuming an allowable contribution of 0.75% (1.5% peak-to-peak) from the voltage loop to the total harmonic distortion budget sets the gain equal to: G VA + ǒDVVAOUTǓ (0.015) 2 V OPK (24) Where ∆VVAOUT is the effective output voltage range of the error amplifier (5 V for the UCC38500).
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION II. Two Switch Forward DC−to−DC Power Stage A two-switch forward converter topology was selected for the second stage of this design. The two-switch forward power converter has two major advantages over a traditional forward converter, making it ideal for this application.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION output capacitor The following equations can be used to estimate the minimum output capacitance and the capacitor’s maximum allowable equivalent series resistance (ESR), where COUT is the minimum output capacitance and tS is the period of the switching frequency.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION control loop Figure 12 shows the control block diagram for the typical application shown in Figure 9. GC(s) is the compensation network’s transfer function (TF), GOPTO(s) is the opto-isolator TF, GCO(s) is the control-to-output TF, and H(s) is the divider TF.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION Figure 13 shows the circuitry for the voltage feedback loop. D13 is a TL431 shunt regulator that functions as an operational amplifier, providing feedback control. VBOOST VC = VERR VOUT GCO(s) GCO(s) Q5 VREF R36 H11AV1 6 R13 D14 1 5 R16 PGND2 R31 2 4 C14 3 C15 U3 R35 D13 SGND R27 UDG−01091 Figure 13.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 TYPICAL APPLICATION R16 + R13 + VF I TL431 (min) (43) V REF * V VERR (max) I OP (min) (44) To compensate the loop, it is necessary to estimate or measure the control-to-output gain’s frequency response GCO(s). The frequency response for GCO(s) was measured with a network analyzer and the measured frequency response is shown in Figure 15.
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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 23 dB. Therefore the compensation circuitry needs to have a gain of −23 dB at the desired crossover frequency. For this example R35 is calculated at approximately 18.2 kΩ. Capacitor C14 is estimated to be approximately 10 nF and C15 is calculated at approximately 180 pF.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC38501DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 UCC38502DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 UCC38503DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC38501DWTR SOIC DW 20 2000 367.0 367.0 45.0 UCC38502DWTR SOIC DW 20 2000 367.0 367.0 45.0 UCC38503DWTR SOIC DW 20 2000 367.0 367.0 45.
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