Datasheet

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10 11

77777777720

UCC3895

EAN EAP

EAOUT

RAMP

REF

GND

SYNC

DELAB

DELCD ADS

OUTD

OUTC

VCC

PGND

OUTB

OUTA

SS/DISB

A C

OUT

BIAS

UCC1895, UCC2895, UCC3895

www.ti.com

SLUS157P –DECEMBER 1999–REVISED JUNE 2013

BiCMOS Advanced Phase-Shift PWM Controller

Check for Samples: UCC1895, UCC2895, UCC3895

FEATURES

DESCRIPTION

The UCC3895 is a phase-shift PWM controller that

• Programmable-Output Turnon Delay

implements control of a full-bridge power stage by

• Adaptive Delay Set

phase shifting the switching of one half-bridge with

• Bidirectional Oscillator Synchronization

respect to the other. The device allows constant

frequency pulse-width modulation in conjunction with

• Voltage-Mode, Peak Current-Mode, or Average

resonant zero-voltage switching to provide high

Current-Mode Control

efficiency at high frequencies. The part is used either

• Programmable Softstart, Softstop and Chip

as a voltage-mode or current-mode controller.

Disable via a Single Pin

While the UCC3895 maintains the functionality of the

• 0% to 100% Duty-Cycle Control

UC3875/6/7/8 family and UC3879, it improves on that

• 7-MHz Error Amplifier

controller family with additional features such as

enhanced control logic, adaptive delay set, and

• Operation to 1 MHz

shutdown capability. Because the device is built using

• Typical 5-mA Operating Current at 500 kHz

the BCDMOS process, it operates with dramatically

• Very Low 150-μA Current During UVLO

less supply current than it’s bipolar counterparts. The

UCC3895 operates with a maximum clock frequency

APPLICATIONS

of 1 MHz.

• Phase-Shifted Full-Bridge Converters

• Off-Line, Telecom, Datacom and Servers

• Distributed Power Architecture

• High-Density Power Modules

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 BiCMOS Advanced Phase-Shift PWM Controller Check for Samples: UCC1895, UCC2895, UCC3895 FEATURES DESCRIPTION • • • • The UCC3895 is a phase-shift PWM controller that implements control of a full-bridge power stage by phase shifting the switching of one half-bridge with respect to the other.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 RECOMMENDED OPERATING CONDITIONS (1) MIN VDD Supply voltage VDD Supply voltage bypass capacitor (2) CREF Reference bypass capacitor (UCC1895) (3) 0.1 Reference bypass capacitor (UCC2895, UCC3895) CT Timing capacitor (for 500-kHz switching frequency) RT Timing resistor (for 500-kHz switching frequency) (3) RDEL_AB, RDEL_CD Delay resistor (1) (2) (3) (4) MAX UNIT 16.5 V 1.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the UCC1895x. (unless otherwise noted) MIN TYP MAX No-load comparator turn-off threshold PARAMETER TEST CONDITIONS 0.45 0.5 0.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the UCC1895x.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. OUTA 18 O OUTB 17 O OUTC 14 O OUTD 13 O PGND 16 - Output stage ground. RAMP 3 I Inverting input of the PWM comparator. REF 4 O 5 V, ±1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor to ground. Do not use more than 4.7 μF of total capacitance on this pin.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com BLOCK DIAGRAM IRT RT 8 CT 7 Q 8(IRT) OSC Q R SYNC 15 D S Q D S Q Q 6 PWM COMPARATOR RAMP EAP EAN D S Q DELAY C 2 ERROR AMP 20 NO LOAD COMPARATOR + + 1 CURRENT SENSE COMPARATOR 2V CS DELAY B R Q DELAB 17 OUTB 14 DELAY D 12 2.5 V + Q S Q R OUTD 16 PGND 11 ADS 4 REF 5 GND 0.5V 11 V / 9 V REF REFERENCE OK COMPARATOR + 19 HI=ON 4V + 10(IRT) REF RT 13 + 0.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 REF 0.5 V 100 k: 75 k: TO DELAY A AND DELAY B BLOCKS + CS DELAB + 100 k: ADS REF 75 k: TO DELAY C AND DELAY D BLOCKS + DELCD Figure 4. Adaptive Delay Set Block Diagram REF BUSSED CURRENT FROM ADS CIRCUIT 3.5 V DELAB/CD FROM PAD DELAYED CLOCK SIGNAL 2.5 V CLOCK Figure 5.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com DETAILED PIN DESCRIPTION ADS (Adaptive Delay Set) This function sets the ratio between the maximum and minimum programmed output-delay dead time. When the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs when ADS is grounded.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 DELAB and DELCD source about 1 mA maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay is defeated by tying DELAB and, or, DELCD to REF. For an optimum performance keep stray capacitance on these pins at less than 10 pF. EAOUT, EAP, and EAN (Error Amplifier) EAOUT connects internally to the non-inverting input of the PWM comparator and the no-load comparator.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com SS/DISB (Soft-Start/Disable) This pin combines two independent functions. Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V, externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal MOSFET switch.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS OUTPUT DELAY (tDELAY) vs DELAY RESISTANCE (RDEL) OSCILLATOR FREQUENCY (fSW) vs TIMING CAPACITANCE (CT) 2000 1600 1800 1400 1400 1200 1000 800 600 400 1200 1000 800 600 400 200 200 0 0 0 10 20 30 40 Delay Resistance (k 100 1000 Timing Capacitance (pF) C001 C002 Figure 6. Figure 7.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com APPLICATION INFORMATION Programming DELAB, DELCD and the Adaptive Delay Set The UCC2895N allows the user to set the delay between switch commands within each leg of the full-bridge power circuit according to Equation 5. (25 ´ 10 )´ R = -12 DEL tDELAY + 25 NS VDEL (5) From Equation 5 VDEL is determined in conjunction with the desire to use (or not) the ADS feature from Equation 6. VDEL = éë0.75 ´ (VCS - VADS )ùû + 0.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 DELAY TIME vs CURRENT SENSE VOLTAGE A = VADS/VCS RDELAY = 10k A=1.0 DELAY TIME (ns) 500 400 A=0.8 300 A=0.6 200 100 0 0.5 1.0 1.5 A=0.4 A=0.2 A=0.1 2.0 2.5 CURRENT SENSE VOLTAGE (V) Figure 13. Delay Time Under Varying ADS Voltages CLOCK RAMP & COMP PWM SIGNAL OUTPUT A OUTPUT B OUTPUT C OUTPUT D No Output Delay Shown, COMP to RAMP offset not included. Figure 14.
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UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com References 1. M. Dennis, A Comparison Between the BiCMOS UCC3895 Phase Shift Controller and the UC3875, Application Note (SLUA246). 2. L. Balogh, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push--Pull and Bridge Converters, Application Note (SLUA121). 3. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations, Application Note (SLUA107). 4. L.
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UCC1895, UCC2895, UCC3895 www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 REVISION HISTORY Changes from Revision N (May 2009) to Revision O Page • Added thermal information table. .......................................................................................................................................... 2 • Changed REF pin description from “Do not use more than 1.0 μF of total capacitance on this pin.” to “Do not use more than 4.7 μF of total capacitance on this pin.” ..........
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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