Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting Low side HTSSOP 14

Isolation

Amplifier

COMMUNICATION

(Programming & Status Reporting)

141

VDD

PVDD

10OUT2

IN1

AGND

3V3

IN2

CLF

UCD7201PWP

11OUT1

9PGND

ILIM

Bias Supply

Bias Winding

VIN

VOUT

DIGITAL

CONTROLLER

GND

PWMA

ADC4

INTERRUPT or CCR

PWMB

ADC3

VCC

PWM or GPIO

ADC1

ADC2

UCD7201

www.ti.com

SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009

Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable

Common Current Sense

Check for Samples: UCD7201

FEATURES

DESCRIPTION

• Adjustable Current Limit Protection

The UCD7201 is a member of the UCD7K family of

digital control compatible drivers for applications

• 3.3-V, 10-mA Internal Regulator

utilizing digital control techniques or applications

• DSP/μC Compatible Inputs

requiring fast local peak current limit protection.

• Dual ±4-A TrueDrive™ High Current Drivers

The UCD7201 includes dual low-side ±4-A

• 10-ns Typical Rise and Fall Times with 2.2-nF

high-current MOSFET gate drivers. It allows the

Loads

digital power controllers such as UCD9110 or

• 20-ns Input-to-Output Propagation Delay

UCD9501 to interface to the power stage in double

ended topologies. It provides a cycle-by-cycle current

• 25-ns Current Sense-to-Output Propagation

limit function for both driver channels, a

Delay

programmable threshold and a digital output current

• Programmable Current Limit Threshold

limit flag which can be monitored by the host

• Digital Output Current Limit Flag

controller. With a fast cycle-by-cycle current limit

protection, the driver can turn off the power stage in

• 4.5-V to 15-V Supply Voltage Range

the event of an overcurrent condition.

• Rated from -40°C to 105°C

For fast switching speeds, the UCD7201 output

stages use the TrueDrive™ output architecture, which

APPLICATIONS

delivers rated current of ±4 A into the gate of a

• Digitally Controlled Power Supplies

MOSFET during the Miller plateau region of the

• DC/DC Converters

switching transition. It also includes a 3.3-V, 10-mA

• Motor Controllers

linear regulator to provide power to the digital

• Line Drivers controller.

TYPICAL APPLICATION DIAGRAM (Push-Pull Converter)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TrueDrive, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable Common Current Sense Check for Samples: UCD7201 FEATURES DESCRIPTION • • • • • The UCD7201 is a member of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. 1 2 • • • • • • Adjustable Current Limit Protection 3.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONT.) For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input line, the UCD7601 includes a 110-V high-voltage startup circuit.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) SYMBOL VDD (2) PARAMETER UCD7201 UNIT 16 V Supply Voltage Quiescent 20 Switching, TA = 25°C, , TJ = 125°C, VDD = 12 V 200 IDD Supply Current VOUT Output Gate Drive Voltage OUT Output Gate Drive Current OUT IOUT(sink) IOUT(source) Analog Input mA -1 to PVDD 4.0 A -4.0 ISET, CS -0.3 to 3.6 ILIM -0.3 to 3.6 Digital I/O’s IN, CLF -0.3 to 3.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, 4.7-μF capacitor from VDD to GND, 0.22μF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 0.51 0.55 0.58 1.05 1.10 1.15 UNIT CURRENT LIMIT (ILIM) ILIM internal current limit threshold ILIM = OPEN ILIM maximum current limit threshold ILIM = 3.3 V ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 FUNCTIONAL BLOCK DIAGRAM NC 1 3V3 2 IN1 3 AGND 4 IN2 5 CLF 6 3V3 Regulator UVLO NC 13 VDD 12 PVDD 11 OUT1 10 OUT2 9 PGND 8 CS + and Reference 14 + Q SD 25 mV R Q ILIM R 7 Figure 1.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com TERMINAL FUNCTIONS UCD7201 PIN NAME I/O - NC - No Connection 2 1 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22 μF of ceramic capacitance from this pin to ground. 3 2 IN1 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 APPLICATION INFORMATION The UCD7201 is member of the UCD7K family of digital compatible drivers targeting applications utilizing digital control techniques or applications that require local fast peak current limit protection. Supply The UCD7K devices accept a supply range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD input.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com The CS threshold is 25 mV below the ILIM voltage. If the user attempts to command zero current while the CS pin is at ground the CLF flag will latch high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin will always be greater than the CS pin for the handshaking to work as described below.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. With VDD = 12 V, CLOAD = 2.2 nF, and f = 300 kHz, the power loss can be calculated as: P + 2.2 nF 122 300 kHz + 0.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com Additional Application Circuits Figure 2 shows the UCD7201 in a half-bridge converter design. The digital controller is performing the output voltage compensation and all supervisory functions. The isolation amplifier is made up of a linear opto-coupler configured for a gain of 1/10, so the output voltage is transformed to a level comparable with the ADC of the digital controller.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 Typical Characteristics UVLO THRESHOLDS vs TEMPERATURE 3V3 REFERENCE VOLTAGE vs TEMPERATURE 5.0 3.36 UVLO on 4.5 3.34 UVLO off 3V3 − Reference Voltage − V VUVLO − UVLO Thresholds − V 4.0 3.5 3.0 2.5 2.0 1.5 3.32 3.30 3.28 1.0 3.26 0.5 0.0 −50 UVLO hysteresis 3.24 −25 0 25 50 75 100 125 −50 t − Temperature − °C 0 25 50 75 t − Temperature − °C Figure 4. Figure 5.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com SUPPLY CURRENT vs FREQUENCY (VDD = 10 V) 280 320 240 280 CLOAD = 10 nF IDD − Supply Current − mA IDD − Supply Current − mA SUPPLY CURRENT vs FREQUENCY (VDD = 8 V) 200 160 CLOAD = 4.7 nF 120 80 240 CLOAD = 10 nF 200 160 CLOAD = 4.7 nF 120 80 CLOAD = 2.2 nF 40 CLOAD = 2.2 nF 40 CLOAD = 1 nF 0 0 500 0 1500 1000 CLOAD = 1 nF 0 500 Figure 8. Figure 9.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 INPUT THRESHOLDS vs TEMPERATURE OUTPUT RISE TIME AND FALL TIME vs TEMPERATURE (VDD = 12 V) 2.5 18.0 CLOAD = 2.2 nF 16.0 tR, tF − Rise and Fall Times − ns Input Rising VINPUT − Input Voltage − V 2.0 1.5 Input Falling 1.0 tR = Rise Time 14.0 12.0 10.0 tF = Fall Time 8.0 6.0 4.0 0.5 2.0 0.0 0.0 −50 −25 0 25 50 75 100 −50 125 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 12.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com IN to OUTx PROPAGATION DELAY RISING vs SUPPLY VOLTAGE IN to OUTx PROPAGATION DELAY FALLING vs SUPPLY VOLTAGE 25 tPD − Propagation Delay, Falling − ns tPD − Propagation Delay, Rising − ns 20 CLOAD = 10 nF 15 10 CLOAD = 4.7 nF 5 CLOAD = 2.2 nF CLOAD = 10 nF 20 15 CLOAD = 4.7 nF 10 CLOAD = 2.2 nF CLOAD = 1 nF CLOAD = 1 nF 5 0 5 7.5 10 12.5 15 5 7.5 Figure 16. Figure 17.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 CS TO CLF PROPAGATION DELAY vs TEMPERATURE IN TO OUT PROPAGATION DELAY vs TEMPERATURE 35 50 30 40 tPD − Propagation Delay − ns tPD − CS to CLF Propagation Delay − ns 45 35 30 25 20 15 10 25 20 15 10 5 5 0 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 20. Figure 21.
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UCD7201 SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 www.ti.com START-UP BEHAVIOR AT VDD = 12 V (INPUT SHORTED TO GND) SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT SHORTED TO GND) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div t − Time − 40 µs/div Figure 24. Figure 25. Output Voltage − 2 V/div OUTPUT RISE AND FALL TIME (VDD = 12 V, CLOAD = 10 nF) t − Time − 40 ns/div Figure 26.
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UCD7201 www.ti.com SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009 REFERENCES 1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCD7201PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 14 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7201PWPR HTSSOP PWP 14 2000 367.0 367.0 35.
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