Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers VQFN 20

Curre nt

Limit Logic

ILIM

CLF

AGND

3V3

REG

Driv e andDead-Time

ControlLogic

(D;1-D)

UVLO

DLY

BIAS

CS+ BST OUT1 SW PVDD OUT2 PGND

Enable

0.6 V

POS

NEG

VDD

ILIM/10

48x

Over

Curre nt

SRE

Blank

UCD7230

DLY

LOAD

PWM

SRE

OUT

DLY

BIAS

MAX

CLF

UCD7230

www.ti.com

SLUS741D –NOVEMBER 2006–REVISED JANUARY 2010

Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense

Conditioning Amplifier

Check for Samples: UCD7230

FEATURES

APPLICATIONS

• Digitally-Controlled Synchronous-Buck Power

• Input from Digital Controller Sets Operating

Stages for Single and Multi-Phase

Frequency and Duty Cycle

Applications

• Up to 2-MHz Switching Frequency

• Especially Suited for Use with UCD91xx or

• Dual Current Limit Protection with

UCD95xx Contollers

Independently Adjustable Thresholds

• High-Current Multi-Phase VRM/EVRD

• Fast Current Sense Circuit with Adjustable

Regulators for Desktop, Server, Telecom and

Blanking Interval Prevents Catastrophic

Notebook Processors

Current Levels

• Digitally-Controlled Synchronous-Buck Power

Supplies Using mCs or the TMS320TM DSP

• Digital Output Current Limit Flag

Family

• Low Offset, Gain of 48, Differential Current

Sense Amplifier

DESCRIPTION

• 3.3-V, 10-mA Internal Regulator

The UCD7230 is part of the UCD7K family of digital

• Dual TrueDrive™ High-Current Drivers

control compatible drivers for applications utilizing

• 10-ns Typical Rise/Fall Times with 2.2-nF

digital control techniques or applications requiring fast

Loads

local peak current limit protection.

• 4.5-V to 15.5-V Supply Voltage Range

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TrueDrive, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
UCD7230 www.ti.
PAGE 2
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com The UCD7230 is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD95xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230 device protects the power stage from faulty input signals or excessive load currents.
PAGE 3
UCD7230 www.ti.
PAGE 4
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com 3V3 17 16 15 SW UCD7230 (QFN RGW) (5x5, 0.
PAGE 5
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VDD CONDITION 16 Supply voltage BST IDD Supply current VO Output gate drive voltage VALUE SW + 16 Quiescent 20 Switching, TA = 25°C, VDD = 12 V 200 OUT1, BST OUT2 -1 V to 36 -1 V to VDD+0.3 IOUT(sink) OUT1 4.0 IOUT(source) OUT1 -2.0 OUT2 4.
PAGE 6
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 500 700 mA 5 8 mA SUPPLY Supply current, off VDD = 4.
PAGE 7
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX RDLY = 24.3 kΩ (CSBIAS-CS+) 170 235 300 RDLY = 49.
PAGE 8
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted).
PAGE 9
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL UCD7230 NAME I/O DESCRIPTION HTSSOP20 QFN-20 VDD 1 18 - Supply input pin to power the internal circuitry except the driver outputs. The UCD7230 accepts an input range of 4.5 V to 15.5 V. SRE 2 19 I Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V logic level signals, used to disable the synchronous rectifier switch.
PAGE 10
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com APPLICATION INFORMATION Introduction The UCD7230 is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications that require local fast peak current limit protection.
PAGE 11
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 Driver Stages The driver outputs utilize Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides best switching speeds and reduces switching losses. TrueDrive™ consists of pull-up/ pull-down circuits using bipolar and MOSFET transistors in parallel.
PAGE 12
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com Current Sensing and Overload Protection Since the UCD7230 is physically collocated with the high-current elements of the power converter, it is logical that current be monitored by the chip. An internal instrumentation amplifier conditions current sense signals so that they can be used by the control chip generating the PWM signal. POS and NEG are inputs to an instrumentation amplifier circuit.
PAGE 13
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 With the addition of RPOS and RNEG, the natural gain, A, of the current sense is predictably decreased as: A= 48 æ RPOS ö 1+ ç ÷ è 8.33 k W ø (3) For RPOS << 8.33 kΩ, the gain is 48. While the 400 kΩ and 8.33 kΩ are well matched, it is important to keep RPOS as small as possible since they have absolute variation from chip-to-chip and over temperature. The graph in Figure 6 shows the band of expected gain for A as a function of RPOS.
PAGE 14
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com The amp output can go up to 3.3 V, so reasonable designs limits full scale to 3.0 V. Should attenuation be necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 7. To A/D A0 Figure 7.
PAGE 15
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 A) GPIO Outputs DIGITAL CONTROLLER UCD7230 VCC 3V3 GND AGND 40 kW ILIM GPIO1 20 kW GPIO2 ILIM SETPOINT [Volts] ILIM (open) 0.50 ILIM0 0.00 ILIM1 0.14 ILIM2 0.29 ILIM3 0.43 ILIM4 0.57 ILIM5 0.72 ILIM6 0.86 ILIM7 1.00 10 kW GPIO3 2.
PAGE 16
UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com If either comparator threshold is exceeded, OUT1 is immediately turned off for the remainder of the cycle and CLF is asserted true. Upon the rising edge of IN, the switches resume normal operation, but the CLF assertion is maintained. If a fault is not detected in this switching cycle, then the next rising edge of IN removes the CLF assertion. However, if one of the comparators detects a fault, then CLF assertion continues.
PAGE 17
UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 REFERENCES 1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by Laszlo Balogh, Texas Instruments Literature No. SLUP224 2. Power Supply Seminar SEM–1400 Topic 2: Design and Application Guide for High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) UCD7230PWPR HTSSOP PWP 20 2000 330.0 16.4 UCD7230RGWR VQFN RGW 20 3000 330.0 UCD7230RGWR VQFN RGW 20 3000 330.0 UCD7230RGWT VQFN RGW 20 250 UCD7230RGWT VQFN RGW 20 250 6.95 7.1 1.6 8.0 16.0 Q1 12.4 5.25 5.25 1.1 8.0 12.0 Q2 12.4 5.3 5.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7230PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 UCD7230RGWR VQFN RGW 20 3000 370.0 355.0 55.0 UCD7230RGWR VQFN RGW 20 3000 367.0 367.0 35.0 UCD7230RGWT VQFN RGW 20 250 210.0 185.0 35.0 UCD7230RGWT VQFN RGW 20 250 195.0 200.0 45.
PAGE 20
PAGE 21
PAGE 22
PAGE 23
PAGE 24
PAGE 25
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.