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BP3GND

MON

PWM-B

SRE-B

FLT-B

V DIS

I -B

MON

BST-B

BSW-B

SW-B

PGND

PWM-A

SRE-A

FLT-A

I -A

MON

BST-A

BSW-A

SW-A

PGND

UCD7242

www.ti.com

SLUS962B –JANUARY 2010–REVISED AUGUST 2012

Digital Dual Synchronous-Buck Power Driver

Check for Samples: UCD7242

FEATURES

APPLICATIONS

• Fully Integrated Power Switches With Drivers • Digitally-Controlled Synchronous-Buck Power

for Dual Synchronous Buck Converters Stages

• Full Compatibility With TI Fusion Digital Power • High Current Dual-Phase VRM/EVRD

Supply Controllers, Such as the UCD92xx Regulators for Desktop, Server, Telecom and

Family Notebook Processors

• Wide Input Voltage Range: 4.75 V to 18 V

Operational Down to 2.2 V Input With an

External Bias Supply

• Up to 10A Output Current per Channel

• Operational to 2 MHz Switching Frequency

• High Side Current Limit With Current Limit

Flag

• Onboard Regulated 6 V Driver Supply From V

• Thermal Protection

• Temperature Sense Output – Voltage

Proportional to Chip Temperature

• UVLO and OVLO Circuits Ensure Proper Drive

Voltage

• Rated From –40°C to 125°C Junction

Temperature

• RoHS Compliant

• Accurate On-Die Current Sensing (±5%)

DESCRIPTION

The UCD7242 is a complete power system ready to drive two independent buck power supplies (see Figure 1).

High side MOSFETs, low side MOSFETs, drivers, current sensing circuitry and necessary protection functions

are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits

provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous

rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6.25 V by an internally regulated V

supply. The internal V

regulator can be disabled to permit the user to supply an independent gate drive

voltage. This flexibility allows a wide power conversion input voltage range of 2.2V to 18V. Internal under voltage

lockout (UVLO) logic ensures V

is good before allowing chip operation.

The synchronous rectifier enable (SRE) pin controls whether or not the low-side MOSFET is turned on when the

PWM signal is low. When SRE is high the part operates in continuous conduction mode for all loads. In this

mode the drive logic block uses the PWM signal to control both the high-side and low-side gate drive signals.

Dead time is also optimized to prevent cross conduction. When SRE is low, the part operates in discontinuous

conduction mode at light loads. In this mode the low-side MOSFET is always held off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 Digital Dual Synchronous-Buck Power Driver Check for Samples: UCD7242 FEATURES APPLICATIONS • • 1 • • • • • • • • • • • • Fully Integrated Power Switches With Drivers for Dual Synchronous Buck Converters Full Compatibility With TI Fusion Digital Power Supply Controllers, Such as the UCD92xx Family Wide Input Voltage Range: 4.75 V to 18 V Operational Down to 2.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) On-board comparators monitor the current through the high side switch to safeguard the power stage from sudden high current loads.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 ORDERING INFORMATION OPERATING TEMPERATURE RANGE, TA PIN COUNT –40°C to 125°C 32-pin ORDERABLE PART NUMBER SUPPLY UCD7242RSJR Reel of 2500 UCD7242RSJT Reel of 250 PACKAGE TOP SIDE MARKING QFN UCD7242 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VIN Supply voltage BST Boot voltage VGG, VGG_DIS Gate supply voltage BP3 Logic supply voltage DC RATING VALUE –0.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY SECTION Supply current Outputs not switching, VIN = 2.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT THERMAL SENSE Thermal shutdown (2) 170 Thermal shutdown hysteresis (2) °C 20 °C 10 mV/°C 470 mV 32 ns High side MOSFET RDS(ON) 15.5 mΩ Low side MOSFET RDS(ON) 6.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com PIN FUNCTIONS UCD7242 –BUCK POWER STAGE QFN PIN NAME I/O FUNCTION High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of the high side MOSFET and the low side MOSFET when SRE-B is high. 1 I PWM = high PWM = low PWM = 1.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 PIN FUNCTIONS (continued) UCD7242 –BUCK POWER STAGE QFN PIN NAME I/O FUNCTION 25 SRE-A I Synchronous Rectifier Enable input for the A-channel. High impedance digital input capable of accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate anti-cross-conduction delay is used during synchronous mode. High impedance digital input capable of accepting 3.
PAGE 8
UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. UCD7242 Efficiency - % 90 85 VO = 3.3 V, fs = 500 kHz, VI = 8 V VO = 3.3 V, fs = 750 kHz, VI = 8 V VO = 3.3 V, fs = 1 MHz, VI = 8 V VO = 2 V, fs = 500 kHz, VI = 8 V 80 VO = 2 V, fs = 750 kHz, VI = 8 V VO = 2 V, fs = 1 MHz, VI = 8 V VO = 1.2 V, fs = 500 kHz, VI = 8 V 75 VO = 1.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. UCD7242 Efficiency - % 90 85 VO = 3.3 V, fs = 500 kHz, VI = 10 V VO = 3.3 V, fs = 750 kHz, VI = 10 V VO = 3.3 V, fs = 1 MHz, VI = 10 V VO = 2 V, fs = 500 kHz, VI = 10 V 80 VO = 2 V, fs = 750 kHz, VI = 10 V 75 VO = 2 V, fs = 1 MHz, VI = 10 V VO = 1.2 V, fs = 500 kHz, VI = 10 V VO = 1.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. UCD7242 90 Efficiency - % 85 80 VO = 3.3 V, fs = 500 kHz, VI = 12 V VO = 3.3 V, fs = 750 kHz, VI = 12 V VO = 3.3 V, fs = 1 MHz, VI = 12 V VO = 2 V, fs = 500 kHz, VI = 12 V 75 VO = 2 V, fs = 750 kHz, VI = 12 V 70 VO = 2 V, fs = 1 MHz, VI = 12 V VO = 1.2 V, fs = 500 kHz, VI = 12 V VO = 1.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. UCD7242 90 Efficiency - % 85 80 75 VO = 3.3 V, fs = 500 kHz, VI = 14 V VO = 3.3 V, fs = 750 kHz, VI = 14 V VO = 3.3 V, fs = 1 MHz, VI = 14 V VO = 2 V, fs = 500 kHz, VI = 14 V 70 VO = 2 V, fs = 750 kHz, VI = 14 V VO = 2 V, fs = 1 MHz, VI = 14 V VO = 1.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. UCD7242 1 Rail Operating 50 IGG - mA fs = 2000 kHz 40 fs = 1500 kHz 30 fs = 1000 kHz 20 fs = 500 kHz 10 fs = 0 kHz 0 4 4.5 5 5.5 6 6.5 VGG - V Figure 10.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient. Continuous Operation at IOUT = 10A 10 7 5 MTTF - Years TJ = 150°C 3 TJ = 140°C 2 TJ = 130°C TJ = 120°C 1 TJ = 110°C 0 20 30 50 Duty Cycle - % 70 100 Figure 12.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION PWM INPUT The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET on time. This input is designed to accept 3.3V logic levels, but is also tolerant of 5V input levels. The SRE pin sets the behavior of the PWM pin. When the SRE pin is asserted high, the device is placed in synchronous mode.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 VGG_DIS This pin, when asserted high, disables the on-chip VGG linear regulator. When tied low, the VGG linear regulator is used to derive VGG from VIN. This pin is designed to be permanently tied high or low depending on the power architecture being implemented. It is not intended to be switched dynamically while the device is in operation. SW The SW pin is the switching node of the power conversion stage.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com IMON MOSFET current sense monitor output. This pin provides a current source output that is proportional to the current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should be connected to a resistor to GND to produce a voltage proportional to the power-stage load current. For example, a value of 10kΩ to ground produces a voltage of 2.0V when the power stage current is 10A.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 2.0 1.8 1.6 TMON - V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TJ - Junction Temperature - °C Figure 15. Typical Characteristics If the junction temperature exceeds approximately 170°C, the device will enter thermal shutdown. This will assert the FLT pin, both MOSFETs will be turned off and the switch node will go high impedance.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION A partial schematic of a power supply application using the UCD7242 power stage is provided below. Although not shown the IC controlling the output is from the UCD92XX family of digital controllers.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 OPERATING FREQUENCY Switching frequency is a key place to start the design of any DC/DC converter. This will set performance limits on things such as: maximum efficiency, minimum size, and achievable closed loop bandwidth. A higher switching frequency is, generally, going to yield a smaller design at the expense of a lower efficiency.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com V - VOUT D L = 5 IN 2 ´ IOUT ¦s (5) For example, plotting this result as a function of VIN and VOUT results in: Figure 17. Inductance vs. VIN and VOUT In this graph IOUT is 10A, the switching frequency is 750kHz and the inductor ΔI is 4A. If the switching frequency is cut in half then the resulting inductance would be twice the value shown. Notice that the maximum inductance occurs at the maximum VIN and VOUT shown on the plot.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 Powdered iron has the advantage of lower cost and a soft saturation characteristic; however, its losses can be very large as switching frequencies increase. This can make it undesirable for a UCD7242 based application where higher switching frequency may be desired. It’s also worth noting that many powdered iron cores exhibit an aging characteristic where the core losses increase over time.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com IOUT 10A ILRMS 10A ΔI 4A IMAX 13.8A Armed with this data one can now approach the inductor data sheet to select a part with a “saturation” limit above 13.8A and current “heating” limit above 10A. Furthermore, total losses can be estimated based on the datasheet DCR value (ILRMS 2DCR) and the core loss curves for a given frequency and ΔI.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 The term in this equation multiplied by the esr gives the ripple voltage component due to esr and the term multiplied by 1/C gives the ripple voltage component due to the change in charge on the capacitor plates.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Vin + 330uF PWM1 26 PWM-A Vin 29 SRE1 25 SRE-A NC 28 EAp1 22uF 25V 18 FLT-A CS1 SN74LVC1G32 FF1 Vin 27 20 IMON-A SW-A 14 1 PWM-B BST-A 24 2 SRE-B BSW-A 23 9 FLT-B PGND 15 7 IMON-B 10r0 800nH Vout1 + 0.22uF 47uF 330uF GND NC 16 10r0 Temp 19 TMON EAn1 PGND 17 Vin 30 4k99 UCD7242 NC 31 22uF 25V Vin 32 1uF 22 VDD 21 AGND BST-B 3 BSW-B 4 5 VGG 4.7uF 6 VGG DIS 8 Test 800nH SW-B 13 0.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 VIN C32 TP31 CS3 TP32 FF3 TP33 SRE3 22uF 25V 1210 TP34 PWM3 PWM3 26 PWM-A Vin 29 SRE3 25 SRE-A Vin 28 C8 FF3 18 FF-A CS3 Vin 27 20 Isense-A SW-A 14 PWM4 1 PWM-B BST-A 24 SRE4 2 SRE-B BSW-A 23 FF4 9 FF-B PGND 15 CS4 7 Isense-B PGND 16 19 Tsense PGND 17 T2 T2 TP35 CS4 TP36 FF4 TP37 R36 10k0 0603 SRE4 TP38 PWM4 TP39 R35 10k0 0603 R37 10k0 0603 C30 4.7uF 0805 TP46 SW3 EAp3 L1 800nH HM00-08822LF 12.
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UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Output cap PGND PGND VIN Input caps PGND PGND Output cap Figure 20.
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UCD7242 www.ti.com SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 Note how the ground end of the VIN and VOUT caps and the PGND stripes of the UCD7242 are all tied together with multiple vias. Note: This is the primary heat dispersal layer as well as the major return-current path. Figure 21. Layer 2 - Power GND Plane Figure 22.
PAGE 28
UCD7242 SLUS962B – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com C32 is another VIN bypass cap placed directly under the part. Note use of multiple vias to tie directly to the VIN and PGND stripes. Figure 23. Bottom Layer (X-ray View) Spacer REVISION HISTORY Changes from Original (January 2010) to Revision A • Page Changed Figure 20 through Figure 23 ...............................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD7242RSJR QFN RSJ 32 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD7242RSJT QFN RSJ 32 250 180.0 16.4 6.3 6.3 1.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7242RSJR QFN RSJ 32 2500 367.0 367.0 38.0 UCD7242RSJT QFN RSJ 32 250 210.0 185.0 35.
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