Datasheet

BROWNOUT
I
2
C INTERFACE
I
2
C Address Selection
I
2
C Transactions
UCD9080
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The UCD9080 can also be configured to sequence the entire system in response to a sustained error condition.
When the UCD9080 monitors an alarm event on the configured rail, UCD9080 RESET occurs (all ENx and
GPOx outputs go to the high-impedance state for ~4 – 5 ms). Next, a sequence of all configured enables and
GPOs occurs, as defined by the current sequencer configuration. Note that for this configuration, a shutdown
according to the values in the UnsequenceTime register does not occur prior to UCD9080 RESET.
The UCD9080 can also be configured to attempt to restart a rail once in response to a sustained error condition.
When the UCD9080 monitors an alarm event on a configured rail, the rail is momentarily disabled and then
re-enabled. The rail remains enabled according to the RampTime register setting (time), and if the rail does not
properly achieve regulation, the system (rail and dependent rails) is shut down as defined by the current
sequencer configuration (UnsequenceTime register).
The last option that the UCD9080 supports is to shut down (if specified as a dependency) and disable (Retry 0
times) a configured rail in response to a sustained error condition. When the UCD9080 monitors an alarm event
on the configured rail, the system (dependent rails and GPOs) is shut down as defined by the current sequencer
configuration (UnsequenceTime register). Only rails and GPOs marked as dependencies of the configured rail
are shut down. If there are no rails or GPO dependencies marked, the configured rail is just disabled in response
to the sustained error condition.
Each UCD9080 ENx and GPOx output can be marked to sequence after shutdown (as defined by the current
sequencer configuration) if specified as a dependency in the DependencyMasks register. For example, if rail 1 is
configured to sequence after shutdown (RESEQ bit set), and rail 2 has rail 1 set in its dependency mask, then
if/when rail 2 is shut down, rail 1 shuts down and the system resequences.
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
The UCD9080 power-supply sequencer has a 100-kHz, slave-mode I
2
C interface for communication with an I
2
C
master. The I
2
C master uses this interface to configure and monitor the UCD9080.
The UCD9080 supports 7-bit I
2
C addressing. The UCD9080 selects an I
2
C address by sampling the logic level of
the four digital inputs to the device (ADDR1 – ADDR4) during the UCD9080 RESET interval. When the UCD9080
is released from RESET, the ADDRx logic levels are latched and the I
2
C address is assigned as shown in
Figure 8 .
A
A
A7 = 1 A6 = 1 A5 = 0 A4 = ADDR4/GPO4 A3 = ADDR3/GPO3 A2 = ADDR2/GPO2 A1 = EN8/ADDR1/GPO1
Figure 8. I
2
C ADDRESS = 0x60 – 0x6F
External pullup/pulldown resistors are required to configure the I
2
C address; the UCD9080 does not have internal
bias resistors. Note that the 7-bit I
2
C address refers to the address bits only, not the read/write (8
th
) bit in the first
byte of the I
2
C protocol. The base I
2
C address is 0x60 and the I
2
C general-call address (0x00) is not supported.
After the initialization process of the UCD9080 is complete, these four pins can be used as general-purpose
outputs (GPOs). They can be programmed and sequenced as described in the Configuring the UDC9080
section. GPO polarity must consider the external I
2
C address resistors as described in the External
Considerations for EN and GPO Pins section.
The UCD9080 can be configured and monitored via I
2
C memory-mapped registers. Registers that are
configurable (can be written) via an I
2
C write operation are implemented using an I
2
C unidirectional data transfer,
from the master to slave, with a stop bit between transactions.
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