Datasheet

STATUS
IICERROR
RAIL
NVERRLOG
RegisterStatus
01234567
rc-0rc-0 rc-0 r r-0 r-0
IICERROR Meaning
0
1
NoI CPHY layererror
2
I CPHY layererror
2
RAIL Meaning
0
1
NoRAIL errorpending
RAIL errorpending
NVERRLOG: Reserved
Register
Status
00
01
10
11
Meaning
Noerror
Invalidaddress
Readaccesserror
Writeaccesserror
r-0
RAILSTATUS
1415 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0
RAIL8
rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0rc-0
RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
RAILnMeaning
0NoalarmpendingforR n
1 AlarmpendingforRAILn
AIL
UCD9080
www.ti.com ................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the
UCD9080. The following bits are defined.
Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the
device is reset. Descriptions of the different errors follow.
The IICERROR bit is set when an I
2
C access fails. This is most often a case where the user has accessed an
invalid address or performed an illegal number of operations for a given register (for example, reading 3 bytes
from a 2-byte register). In the event of an I
2
C error when IICERROR is set, bits 1:0 of the STATUS register
further define the nature of the error as shown in the preceding figure.
The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is
advised to query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The user may
then query the ERROR registers to get further information about the nature of the error condition.
The NVERRLOG bit is reserved for future use.
When the IICERROR bit is set, the register status bits provide further information about the type of I
2
C error that
has been detected, as indicated previously.
The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to
represent the error status of the rails as indicated in the following diagram. The RAILSTATUS1 register is
reserved.
Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a single
16-bit register.
If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the
RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :UCD9080