Datasheet
FLASHLOCK
FLASHLOCK
7
6
5 4
3
2 1
0
rw-0 rw-0
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
FLASHLOCK
0x00 Lockflash(default)
0x01 Flashisbeingupdated
0x02 Unlockflash(beforeconfiguration)
RESTART
WADDR and WDATA
Address
07815
rw-0x00 rw-0x00
WADDR2
(0x31)
WADDR1
(0x30)
UCD9080
SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008 ...................................................................................................................................................
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The FLASHLOCK register is used to lock and unlock the configuration memory on the UCD9080 when updating
the configuration. The Configuring the UDC9080 section details this process.
The format for the FLASHLOCK register is as follows:
The RESTART register provides the capability for the I
2
C host to force a re-initialization and restart of the
UCD9080. This is an 8-bit register, and when a value of 0 is written to the register, the UCD9080 is restarted and
the rails are resequenced.
Note that in order to respond to this I
2
C request properly, there is a 50- µ s delay before the system is restarted,
so that the I
2
C ACK can take place.
In order to update the configuration on the UCD9080, four registers are provided: WADDR2 (address bits 8 – 15),
WADDR1 (address bits 0 – 7), WDATA2 (data bits 8 – 15), and WDATA1 (data bits 0 – 7). WADDR2 and WADDR1
specify the 16-bit memory address and WDATA2 and WDATA1 specify the 16-bit data written to or read from
that memory address.
The format for the WADDR register is as follows:
To set the address of the memory that will be accessed, write the LSB of the address to the WADDR1 register
and the MSB of the address to the WADDR2 register. For example, to write the address 0x1234 to the device,
set WADDR1 = 0x34 and WADDR2 = 0x12. Note that because these addresses support the auto-increment
feature, the user can perform a single 16-bit write to WADDR1 to write the entire address.
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