Datasheet

Data
rw
07815
WDATA2
(0x33)
WDATA1
(0x32)
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CONFIGURING THE UCD9080
I2CWrite:
FLASHSTATE=
UNLOCK(0x02)
I2CWrite:
WADDR=
0xE000
I2CWrite:
WDATA=
0xBADC
I2CWrite:
WADDR=
0xE000
I2CWrite:
WDATA=
Data(16b)
I2CWrite:
WDATA=
Data(16b)
I2CWrite:
FLASHSTATE=
LOCK(0x00)
. . .
16times (32bytes)
- OR-
Repeatas necessary withWADDRupdated
towrite512bytes
UCD9080
www.ti.com ................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
The format for the WDATA register is as follows:
To set the value of the data that will be written, write the LSB of the data to the WDATA1 register and the MSB of
the data to the WDATA2 register. For example, to write the data 0xBEEF to the device, set WDATA1 = 0xEF and
WDATA2 = 0xBE. Note that because these addresses support the auto-increment feature, the user can perform
a single 16-bit write to WDATA1 to write the entire data. To read the value of the data at the specified address,
read the LSB from WDATA1 and the MSB from WDATA2.
These registers are used for updating the UCD9080 configuration as explained in the Configuring the UDC9080
section.
The UCD9080 has many different configurable parameters, such as sequencing policies, shutdown policies and
dependency masks. The UCD9080 can configure all of its parameters via the I
2
C interface while the device is
operational. Sequencing, shutdown, and rail monitoring are not performed during device configuration time.
NOTE:
During runtime, if the UCD9080 is configured, there is a delay in voltage monitoring
while the new configuration parameters are applied to the device.
To configure the UCD9080, a large block of configuration information is sent to the device via the I
2
C interface.
This block is 512 bytes and contains all the configuration information that the device requires for any function of
the UCD9080.
This 512-byte block of configuration information is sent to the device in multiple segments. The segment size can
range from 2 to 32 bytes at one time, and must be a power of 2 bytes. That is, a master can send 256 2-byte
segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper
sequence, and this operation must be completed by sending the last segment so that the last byte of the
512-byte block is written. If this is not done, the UCD9080 is in an unknown state and does not function as
designed.
The process for sending the configuration information to the UCD9080 is as shown in Figure 11 :
Figure 11. Configuration Information
As shown in Figure 11 , the process for updating the configuration of the UCD9080 is as follows:
1. Unlock flash memory by writing the FLASHLOCK register with a value of 0x02.
2. Write the address of the configuration section of memory (WADDR = 0xE000).
3. Write the constant 0xBADC to update memory (WDATA = 0xBADC).
4. Write the address of the configuration section of memory again (WADDR = 0xE000).
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