Datasheet

OutOfRegulationWidth
89101112131415 01234567
OORW
OORW=RAILnout-of-regulationglitch width (inunits of1/10ms).
0 0 00
UnsequenceTime
89101112131415 01234567
USTIME
USTIME=RAILnUnsequenceTime(inunits ofms).
COPYSEQPARAM=Copy SEQPARAMbitvalue
(bits 15:13)inSequenceEventDataregister
COPYSEQPARAM
0
UCD9080
www.ti.com ................................................................................................................................................... SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008
The OutOfRegulationWidth field in the configuration parameters specifies the maximum amount of time that the
rail is allowed to be out of regulation before an error is declared (glitch duration). The address map for these
registers is as follows:
ADDRESS SIZE DEFAULT VALUE DESCRIPTION
0xE140 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 1
0xE142 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 2
0xE144 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 3
0xE146 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 4
0xE148 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 5
0xE14A 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 6
0xE14C 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 7
0xE14E 2 0x0010 The out-of-regulation duration permissible without flagging error for rail 8
The contents of this register are as follows:
The UnsequenceTime field in the configuration parameters specifies the amount of time that each rail should
delay before unsequencing. The address map for these registers is as follows:
ADDRESS SIZE DEFAULT VALUE DESCRIPTION
0xE150 2 0xC0FF Unsequence delay for rail 1
0xE152 2 0xC1FF Unsequence delay for rail 2
0xE154 2 0xC2FF Unsequence delay for rail 3
0xE156 2 0xC3FF Unsequence delay for rail 4
0xE158 2 0xC4FF Unsequence delay for rail 5
0xE15A 2 0xC5FF Unsequence delay for rail 6
0xE15C 2 0xC6FF Unsequence delay for rail 7
0xE15E 2 0xC7FF Unsequence delay for rail 8
0xE160 2 0x0000 Unsequence delay for GPO1
0xE162 2 0xC000 Unsequence delay for GPO2
0xE164 2 0xC000 Unsequence delay for GPO3
0xE166 2 0xC000 Unsequence delay for GPO4
The contents of this register are as follows:
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