Datasheet
UCD9080
SLVS692E – SEPTEMBER 2006 – REVISED MAY 2008 ...................................................................................................................................................
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Changes from Revision D (December 2007) to Revision E ........................................................................................... Page
• Deleted ordering information table ......................................................................................................................................... 2
• Changed NOM and MAX supply current specifications ......................................................................................................... 2
• Updated Schmitt-trigger input signal list to add the ENx pins (inputs during reset) .............................................................. 2
• Removed signal list from high-impedance leakage current specification .............................................................................. 2
• Updated the digital output signal list to include the SCL pin (for clock stretching) ................................................................ 3
• Updated the directionality for the ENx and SCL pins ............................................................................................................ 7
• Clarified wording .................................................................................................................................................................... 9
• Clarified wording in several sentences and removed note at end of paragraph ................................................................... 9
• Moved this section to follow the Power-Supply Enables section. Minor wording change ..................................................... 9
• Added new section to describe ENx and GPOx behavior during device reset, and to describe I
2
C address and
GPOx polarity relationship ..................................................................................................................................................... 9
• Clarified wording in sequence paragraph ............................................................................................................................ 10
• Clarified wording in several paragraphs .............................................................................................................................. 11
• Clarified device time counter reset ...................................................................................................................................... 16
• Clarified FLASHLOCK wording ............................................................................................................................................ 18
• Clarified RESTART wording ................................................................................................................................................ 18
• Clarified WDATA/WADDR wording ...................................................................................................................................... 18
• Clarified wording in several steps ........................................................................................................................................ 19
• Changed pin names from NIC to NC for pins 2, 4, 17, 20, 31............................................................................................. 29
Changes from Revision C (January 2007) to Revision D ............................................................................................... Page
• Changed minimum analog supply and positive built-in reference active V
CC
(min) voltage. Removed minimum
sampling voltage, 1.5-V internal reference, and DCO OPERATING PERIOD specifications. .............................................. 3
• Added specification for data hold time, t
HD;DAT
and notes 3 and 4......................................................................................... 6
• Changed pin #2 from "connect to VSS" to "do not connect" ................................................................................................. 7
• Removed critica-rail-specification sentence from paragraph 4 ............................................................................................ 10
• Added Ignore option and updated available retry options. Updated descriptions of options .............................................. 10
• Added version register and changed WDATA access type from w to rw ........................................................................... 13
• Removed reference to flash and non-volatile error log feature in NVERRLOG bit description ........................................... 17
• Change WDATA access type from w to rw ......................................................................................................................... 19
• Removed Resetting the Flash Error Logs section ............................................................................................................... 19
• Added the UserData section ................................................................................................................................................ 20
• Updated factory byte values ................................................................................................................................................ 20
• Updated factory byte values ................................................................................................................................................ 21
• Removed retry 2, retry 3, retry 4, and retry continuously options ........................................................................................ 24
• Removed SaveRailLog register description ......................................................................................................................... 28
• Removed pin-2 connection to ground .................................................................................................................................. 29
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