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UCD 9081

EN[1:7]

SDA

SCL

VCC

VSS

MON [1:8]

ROSC

RST

XIN

TEST

10kW

100kW

10kW

3.3V

3.3V 3.3V

3.3V

0.01 Fm

1 Fm

OUT1

OUTX

OUT2

SlaveI C

Address

ToI C

MasterDevice

Digital

Outputs

EN8/

ADDR1/

GPO1

ADDR2/

GPO2

ADDR3/

GPO3

ADDR4/

GPO4

Power

Supply

Power

Supply

Power

Supply

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

8-CHANNEL POWER SUPPLY SEQUENCER AND MONITOR WITH ERROR LOGGING

Check for Samples: UCD9081

FEATURES

• Microsoft™ Windows™ GUI for Configuration

and Monitoring

234

• Single Supply Voltage: 3.3V

• Low Power Consumption: 3mA Nominal

APPLICATIONS

Supply Current

• Telecommunications Switches

• Sequences and Monitors Eight Voltage Rails

• Servers

• Rail Voltages Sampled With 3.2-mV Resolution

• Networking Equipment

• Internal or External Voltage Reference

• Test Equipment

• Four Configurable Digital Outputs for

• Industrial

Power-On Reset and Other Functions

• Any System Requiring Sequencing of Multiple

• Configurable Digital Output Polarity

Voltage Rails

• Flexible Rail Sequencing Based On Timeline

(ms), Parent Rail Regulation Window, Or

DESCRIPTION

Parent Rail Achieving Defined Threshold

The UCD9081 power-supply sequencer controls the

• Independent Under- and Overvoltage

enable sequence of up to eight independent voltage

Thresholds Per Rail

rails and provides four general-purpose digital outputs

(GPO). The device operates from a 3.3-V supply,

• Configurable Regulation Expiration Times Per

provides 3.2-mV resolution of voltage rails, and

Rail

requires no external memory or clock. The UCD9081

• Flexible Alarm Processing: Ignore, Log Only,

monitors the voltage rails independently and has a

Retry n Times, Retry Continuously, Sequence,

high degree of rail sequence and alarm response

Parent Rail Can Shutdown Child Rails

options. The sequencing of rails can be based on

timed events or on timed events in conjunction with

• Alarm Conditions Logged With Timestamp:

other rails achieving regulation or a voltage threshold.

Under- and Overvoltage Glitch, Sustained

In addition, each rail is monitored for undervoltage

Under- and Overvoltage, Rail Did Not Start

and overvoltage glitches and thresholds. Each rail the

• On-chip Flash for Storing User Data

UCD9081 monitors can be configured to shut down a

• Error Logging to Flash for System Failure

user-defined set of other rails and GPOs, and alarm

conditions are monitored on a per-rail basis.

Analysis

• I

C™ Interface for Configuration and

Figure 1 shows the UCD9081 power-supply

Monitoring

sequencer in a typical application.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD, TMS320 are trademarks of Texas Instruments.

3Microsoft, Windows are trademarks of Microsoft Corporation.

C is a trademark of Phillips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 8-CHANNEL POWER SUPPLY SEQUENCER AND MONITOR WITH ERROR LOGGING Check for Samples: UCD9081 FEATURES • 1 • Single Supply Voltage: 3.3V • Low Power Consumption: 3mA Nominal Supply Current • Sequences and Monitors Eight Voltage Rails • Rail Voltages Sampled With 3.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com Figure 1. Typical Application Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com Table 1. PIN FUNCTIONS PIN (1) NAME NO. I/O DESCRIPTION ADDR2/GPO2 26 I/O I2C address select 2, general-purpose digital output 2. ADDR3/GPO3 27 I/O I2C address select 3, general-purpose digital output 3. ADDR4/GPO4 28 I/O I2C address select 4, general-purpose digital output 4. EN1 23 I/O Voltage rail 1 enable (digital output). EN2 24 I/O Voltage rail 2 enable (digital output).
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) Voltage applied from VCC to VSS Voltage applied to any pin (2) VALUE UNIT –0.3 to 4.1 V –0.3 to VCC + 0.3 V ±2 mA –40 to 85 °C ESD Diode current at any device terminal Tstg (1) Storage temperature Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MISCELLANEOUS Tretention Retention of configuration parameters POR, BROWNOUT, RESET (see TJ = 25°C 100 Years (2) (3) ) td(BOR) 2000 VCC (start) 0.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 DIGITAL OUTPUTS (only one output is loaded at a time) TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 50 0 VCC = 3 V P1.0 IOH − Typical High-Level Output Current − mA IOL − Typical Low-Level Output Current − mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE o TA = 25 C 40 o TA = 85 C 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 VCC = 3 V P1.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com DIGITAL OUTPUTS (only one output is loaded at a time) (continued) VCC 2 VCC = 3 V tpw 3V Typical Conditions VCC(min) - V 1.5 1 VCC(min) 0.5 0 0.001 1000 1 1 ns tpw - Pulse Width - mS 1 ns tpw - Pulse Width - mS Figure 5. VCC(min) Level with a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 tpw 3V VCC(min) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(min) 0.5 tfall = trise 0 0.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 FUNCTIONAL DESCRIPTION POWER SUPPLY SEQUENCING The UCD9081 can be configured to sequence power supply rails using the enable signals (ENx) or the general-purpose outputs (GPOx) in one of four ways: 1. A rail can be configured to not be sequenced 2. Using a delay time after UCD9081 RESET. The enable/GPO is asserted after UCD9081 RESET plus the user specified delay 3.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 RAIL SHUTDOWN Rail (or GPO) shutdown is the act of setting the ENx (or GPOx) pin to a state which disables the associated power supply output.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com SEQUENCE AFTER SHUTDOWN Sequence after shutdown is an option that can be used in conjunction with Retry n Times . When a fault occurs on the configured rail, this option forces a UCD9081 RESET to occur after the procedure outlined in Retry n Times takes place. Note that if a rail is configured for sequence after shutdown and is forced to shutdown due to a fault on a parent rail, a sequence after shutdown will take place.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 MONITORING THE UCD9081 Register Map The UCD9081 allows all monitoring of the system through the I2C interface on the device. The following is the memory map of the supported registers in the system. The detail of each of these registers is given in the next section as well.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com Register Descriptions The following are the detailed descriptions of each of the UCD9081 I2C registers. The following register bit conventions are used. Each register is shown with a key indicating the accessibility of each bit, and the initial condition after device initialization.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 RAIL For each of eight voltage rails, the UCD9081 has two registers that contain the rolling average voltage for the associated rail as measured by the device. This average voltage is maintained in real-time by the UCD9081 and is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One holds the least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com ERROR Error conditions are logged by the UCD9081 and are accessible to the user via reading the ERROR register.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 STATUS STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the UCD9081. The following bits are defined.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com VERSION The VERSION register provides the user with access to the device revision of the UCD9081. The format of this register is a nibble-based major.minor format as shown below. 7 6 5 4 3 2 r r r Major r r 1 0 r r Minor r RAILSTATUS The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to represent the error status of the rails as indicated in the following diagram.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 WADDR and WDATA In order to update the configuration on the UCD9081, four registers are provided. WADDR2 (address 15:8) and WADDR1 (address bits 7:0) specify the memory address. WDATA2 (data bits 15:8) and WDATA1 (data bits 7:0) specify the data written to or read from that memory address.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com RESETTING THE FLASH ERROR LOG The UCD9081 can be configured to log errors on a critical voltage rail to internal FLASH memory. This mechanism permits the error log to be read after the device has been reset, or if a loss of power causes non-volatile memory to be cleared. As outlined in the section on Error Logging , there are two modes for using this feature.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 CONFIGURING THE UCD9081 The UCD9081 has many different configurable parameters such as sequencing options, alarm processing options, and rail dependencies. A Microsoft™ Windows™ GUI is available for selecting and generating the necessary configuration parameters. To download and install the UCD9081 GUI, see the UCD9081 product folder at http://focus.ti.com/docs/prod/folders/print/ucd9081.html.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com USER DATA User data (128 bytes) can be stored in the UCD9081 FLASH memory at location 0x1080 to 0x10FF. Writes to the User Data section of memory are performed as follows: 1. 2. 3. 4. 5.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 I2C UNIDIRECTIONAL TRANSFER 1 7 1 1 8 1 8 1 1 S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P 0 (write) From master to slave A = acknowledge (SDA low) A = Not acknowledge (SDA high) S = START condition From slave to master P = STOP condition Figure 9.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com I2C TIMING The UCD9081 supports the same timing parameters as standard-mode I2C. See the following timing diagram and timing parameters for more information. SDA tf tLOW tSU;DAT tr tHD;STA tr tBUF tof SCL tHIGH tHD;STA tSU;STA tHD;DAT tSU;STO Sr S P S Figure 11.
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UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 APPLICATION INFORMATION TYPICAL APPLICATION DIAGRAM 330W Status LEDs 25 27 28 26 ADDR3/ G PO3 ADDR4/ G PO4 EN8/ ADDR2/ ADDR1/ G PO1 G PO2 1 VSS SDA 22 21 SCL ROSC NC 4 32 XIN TEST 3 2 EX: Slave I C Address = 0x65 (Internal ADDR[7:5] = 0b110) DNP DNP 1kW 1kW 10kW 10kW 10kW 10kW 3.3V 3.3V VBUS RTN VBUS 3.3V 2 I C Master 3.3V 3.3V 3.3V 3.3V 10kW 10kW 100kW 3.3V Regulator 3.3V 3.3V 10kW 0.01mF 3.
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UCD9081 SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 www.ti.com CONSIDERATIONS FOR MONX INPUT SERIES RESISTANCE, RS RS is the series impedance between the sampled voltage source (low impedance power supply output) and the UCD9081 MONx input pin. This resistance can affect UCD9081 sampling accuracy if it is too large. In most cases (when the power supply being monitored has a lower VOUT than the UCD9081 voltage reference being used) this resistance is low and can be ignored.
PAGE 27
UCD9081 www.ti.com SLVS813B – JUNE 2008 – REVISED DECEMBER 2010 REVISION HISTORY Changes from Original (June 2008) to Revision A Page • Changed the data sheet from Product Preview to Production. Multiple changes throughout. ............................................. 1 • Changed Equation 1, × VREF to VR+ .................................................................................................................................... 15 • Changed Equation 2, × VREF to VR+ .......................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD9081RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 UCD9081RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD9081RHBR VQFN RHB 32 3000 367.0 367.0 35.0 UCD9081RHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.