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Table Of Contents

FEATURES

APPLICATIONS

DESCRIPTION

UCD9240

www.ti.com

................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008

Digital PWM System Controller

• Supported by Fusion Digital Power™

Designer, a Full Featured PC Based Design

• Fully Configurable Multi-Output and

Tool to Simulate, Configure, and Monitor

Multi-Phase Non-Isolated DC/DC PWM

Power Supply Performance.

Controller

• Controls Up To Four Voltage Rails and Up To

Eight Phases

• Industrial/ATE

• Supports Switching Frequencies Up to 2MHz

• Networking Equipment

With 250 ps Duty-Cycle Resolution

• Telecommunications Equipment

• Up To 1mV Closed Loop Resolution

• Servers

• Hardware-Accelerated, 3-Pole/3-Zero

• Storage Systems

Compensator With Non-Linear Gain for

• FPGA, DSP and Memory Power

Improved Transient Performance

• Supports Multiple Soft-Start and Soft-Stop

Configurations Including Prebias Start-up

The UCD9240 is a multi-rail, multi-phase

• Supports Voltage Tracking, Margining and

synchronous buck digital PWM controller designed for

Sequencing

non-isolated DC/DC power applications. This device

• Supports Current and Temperature Balancing

integrates dedicated circuitry for DC/DC loop

for Multi-Phase Power Stages

management with flash memory and a serial interface

to support configurability, monitoring and

• Supports Phase Adding/Shedding for

management.

Multi-Phase Power Stages

• Sync In /Out Pins Align DPWM Clocks

The UCD9240 was designed to provide a wide

variety of desirable features for non-isolated DC/DC

Between Multiple UCD9240 Devices

converter applications while minimizing the total

• Fan Monitoring and Control

system component count by reducing external

• 12-Bit Digital Monitoring of Power Supply

circuits. The solution integrates multi-loop

Parameters Including:

management with sequencing, margining, tracking

and intelligent phase management to optimize for

– Input Current and Voltage

total system efficiency. Additionally, loop

– Output Current and Voltage

compensation and calibration are supported without

– Temperature at Each Power Stage

the need to add external components.

• Multiple Levels of Overcurrent Fault

To facilitate configuring the device, the Texas

Protection:

Instruments Fusion Digital Power™ Designer is

– External Current Fault Inputs

provided. This PC based Graphical User Interface

offers an intuitive interface to the device. This tool

– Analog Comparators Monitor Current

allows the design engineer to configure the system

Sense Voltage

operating parameters for the application, store the

– Current Continually Digitally Monitored

configuration to on-chip non-volatile memory and

• Over and Undervoltage Fault Protection

observe both frequency domain and time domain

simulations for each of the power stage outputs.

• Overtemperature Fault Protection

• Enhanced Nonvolatile Memory With Error

TI has also developed multiple complementary power

stage solutions – from discrete drives in the UCD7k

Correction Code (ECC)

family to fully tested power train modules in the PTD

• Device Operates From a Single Supply With an

family. These solutions have been developed to

Internal Regulator Controller That Allows

complement the UCD9k family of system power

Operation Over a Wide Supply Voltage Range

controllers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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UCD9240 www.ti.com...................................................................................................................................................
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SUPPLY CURRENT IV33A VV33A = 3.3 V 8 15 IV33DIO VV33DIO = 3.3 V 2 10 VV33D = 3.3 V 40 45 VV33D = 3.3 V storing configuration parameters in flash memory TBD 50 55 3.3 3.35 4 4.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Dgnd +0.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power stage's ouput current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage).
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com HARDWARE FAULT DETECTION LATENCY The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer. PARAMETER TEST CONDITIONS MAX TIME UNIT 15 + 3 × NumPhases µs Step change in CS voltage from 0v to 2.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 The coefficients of the filter sections are generated through modeling the power stage and load in the Power+ Designer tool. Several banks of filter coefficients can be downloaded to the device that can automatically switch them based on the power stage operation. Figure 1.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.
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UCD9240 15 16 27 28 39 FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A AddrSens0 AddrSens1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B Vin/Iin Vtrack Temp SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A 11 12 13 14 25 34 22 24 33 35 29 30 AVSS-1 AVSS-2 49 48 64 8 26 43 70 58 57 8 56 59 62 63 64 65 66 67 68 69 77 76 75 4 3 2 79 78 74 73 5 6 7 72 71 1 EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 V33FB V33A V33D V33DIO-1 V33DIO-2 BPCap 17 18 19 20 21 23 31 TMUX-0 32 TMUX-1 PMBus
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com TYPICAL APPLICATION SCHEMATIC Figure 3 shows the UCD9240 power supply controller as part of a system that provides the regulation of four independent power supplies.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 PIN DESCRIPTIONS 64-PIN PACKAGE PIN NO. SIGNAL 80-PIN PACKAGE PIN NO. SIGNAL I/O DESCRIPTION Error Amplifier Differential Analog Inputs 50 EAp1 62 EAp1 AI Error analog, differential voltage. Positive channel #1 input. 51 EAn1 63 EAn1 AI Error analog, differential voltage.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com PIN DESCRIPTIONS (continued) 64-PIN PACKAGE PIN NO. SIGNAL 80-PIN PACKAGE PIN NO.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 PIN DESCRIPTIONS (continued) 64-PIN PACKAGE PIN NO. SIGNAL 80-PIN PACKAGE PIN NO.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com Table 1. PMBus Address Bins PMBus ADDRESS VPMBus PMBus VOLTAGE RANGE (V) RPMBus PMBus RESISTANCE (kΩ) MIN MAX open 2.226 3.300 – 11 1.746 2.255 210 10 1.342 1.746 158 9 1.030 1.341 115 8 0.792 1.030 84.5 7 0.609 0.792 63.4 6 0.468 0.608 47.5 5 0.359 0.467 36.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 Table 2. PMBus Address Assignment Rules ADDRESS STATUS 0 Prohibited 1-10 Avaliable 11 Avoid 12 Prohibited 13-125 Avaliable 126 Avoid 127 Prohibited REASON SMBus generall address call Causes confilcts with other devices during program flash updates.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com External Reset The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a pull up resistor to 3.3V is recommended.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by the Vref DAC as shown in Figure 7.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the compensator coefficients. The design tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 DPWM Engine (1 of 4) SysClk SyncIn Clk high res reset ramp counter Switch period S PWM gate drive R output Current balance adj Compensator output EADC (calculated duty cycle) trigger EADC trigger threshold SyncOut Figure 10.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com t phase-phase spread = t SW NPhases Where tSW is the switching period and NPhases is the number of power stages driving a voltage rail. DPWM Synchronization DPWM synchronization provides a method to link the timing between rails on two distinct devices at the switching rate; i.e.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 declared and the UCD9240 performs the PMBus configured fault recovery. ADC current measurements are digitally averaged before they are compared against the FAULT threshold. The output current is measured at a rate of one output rail per 200 microseconds.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com Overcurrent Detection Several mechanisms are provided to sense output current fault conditions. This allows for the design of power systems with multiple layers of protection. 1. A logic high signal on the FAULT input causes a hardware interrupt to the internal CPU.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 Input Voltage and Current Monitoring The Vin/Iin pin on the UCD9240 monitors the input voltage and current. To measure both input voltage and input current, an external multiplexer is required.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com Table 5.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the setpoint DAC is adjusted to minimize the error voltage.
PAGE 26
UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com Sequencing There are three methods to squence voltage rails controlled by the UCD9240 that allow for a variety of system sequencing configurations. Each of these options is configurable in the GUI. These methods include: 1. Use the PMBus to set the soft start/stop parameters for each rail.
PAGE 27
UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 GPIO_SEQ_CONFIG allows the configuration of fault relationships such that a fault on one rail can result in the shut down of any selection of rails in addition to the rail at fault.
PAGE 28
UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com Fan Control The UCD9240 can control one fan as defined in the PMBus standard. When enabled, the FAN-PWM control output provides a 156 kHz digital signal, with a duty cycle that is set based on the FAN_COMMAND_1 PMBus command. The duty cycle can be set from 0% to 100% with 1% resolution.
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UCD9240 www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 CONSTANT GAIN COMPONENTS DESCRIPTION Gdelay Phase shift due to the delays in the control loop. Knonlinear Nonlinear function gain. Gain for the limit interval that contains zero error. GCLA2 Transfer function of the second order filter section of the compensator.
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UCD9240 SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com divider Vout R1 EAp Power Stage R2 C2 EAn Figure 16.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD9240PFCR TQFP PFC 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2 UCD9240RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD9240RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD9240PFCR TQFP PFC 80 1000 367.0 367.0 45.0 UCD9240RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD9240RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD9240RGCT VQFN RGC 64 250 210.0 185.0 35.
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MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.