Datasheet

UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................... www.ti.com
PIN DESCRIPTIONS (continued)
64-PIN PACKAGE 80-PIN PACKAGE
I/O DESCRIPTION
PIN NO. SIGNAL PIN NO. SIGNAL
Synchronous Rectification Enable Outputs
22 SRE-1A 12 SRE-1A O Synchronous rectifier enable 1A
24 SRE-1B 11 SRE-1B O Synchronous rectifier enable 1B
33 SRE-2A 51 SRE-2A O Synchronous rectifier enable 2A
35 SRE-2B 37 SRE-2B O Synchronous rectifier enable 2B
29 SRE-3A 38 SRE-3A O Synchronous rectifier enable 3A
52 SRE-3B O Synchronous rectifier enable 3B
30 SRE-4A 33 SRE-4A O Synchronous rectifier enable 4A
50 SRE-4B O Synchronous rectifier enable 4B
Miscellaneous Digital I/O
31 TMUX-0 39 TMUX-0 O Temperature multiplexer select S0
9 RESET 13 RESET I Active low device reset input
32 TMUX-1 40 TMUX-1 O Temperature multiplexer select S1
42 TMUX-2 54 TMUX-2 O Temperature multiplexer select S2
41 FAN-PWM 53 FAN-PWM O Fan control PWM output
39 PowerGood 49 PowerGood O Power good signal (multiplexed with TMS on 64-pin package)
36 FAN-Tach 32 FAN-Tach I Fan tachometer input (multiplexed with TCK on 64-pin package)
Synchronization output from DPWM (multiplexed with TDO on 64-pin
37 Sync_Out 30 Sync_Out O
package)
38 Sync_In 31 Sync_In I Synchronization input to DPWM (multiplexed with TDI on 64-pin package)
10 diag LED O Diagnostic LED
PMBus Communications Interface
15 PMBus_Clk 19 PMBus_Clk I/O PMBus Clk (Must have pullup to 3.3 V)
16 PMBus_Data 20 PMBus_Data I/O PMBus Data (Must have pullup to 3.3 V)
27 PMBus_Alert 35 PMBus_Alert O PMBUS Alert
28 PMBus_Cntrl 36 PMBus_Cntrl I PMBUS Cntl
JTAG
10 TRCK 14 TRCK O Test return clock
36 TCK 44 TCK I Test clock (multiplexed with FAN-Tach (TCK) on 64-pin package)
37 TDO 45 TDO O Test data out (multiplexed with Sync_Out (TDO) on 64-pin package)
Test data in -- tie to Vdd with 10 k Ω resistor (multiplexed with Sync_In
38 TDI 46 TDI I
(TDI) on 64-pin package)
Test mode select -- tie to Vdd with 10 k Ω resistor (multiplexed with
39 TMS 47 TMS I/O
PowerGood (TMS) on 64-pin package)
40 TRST 48 TRST I/O Test reset -- tie to ground with 10 k Ω resistor
Input Power and Grounds
58 V33FB 70 V33FB O 3.3-V linear regulator Feedback connection
46 V33A 58 V33A I Analog 3.3-V supply
45 V33D 57 V33D I Digital core 3.3-V supply
7 V33DIO 8 V33DIO I Digital I/O 3.3-V supply
44 V33DIO 56 V33DIO I Digital I/O 3.3-V supply
47 BPCap 59 BPCap I 1.8-V bypass capacitor connection
49 AV
SS
61 AV
SS
I Analog ground
48 AV
SS
60 AV
SS
I Analog ground
64 AV
SS
80 AV
SS
I Analog ground
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