Datasheet

JTAG Interface
Bias Supply Generator (Series Regulator Controller)
V33FB
V33A
V33D
V33DIO-1 V33DIO-2
BPCap
0.1u
10k0
Vin
4.7u
0.1u
FCX491A
UCD9240
To Power Stage
+3.3V
+1.8V
Power On Reset
UCD9240
www.ti.com ................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
Table 2. PMBus Address Assignment Rules
ADDRESS STATUS REASON
0 Prohibited SMBus generall address call
1-10 Avaliable
11 Avoid Causes confilcts with other devices during program flash updates.
12 Prohibited PMBus alert response protocol
13-125 Avaliable
126 Avoid Default value; may cause conflicts with other devices.
127 Prohibited Used by TI manufacturing for device tests.
The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in
order to enable the fan, sync, and power good status pins with which it is multiplexed. There are three conditions
under which the JTAG interface is enabled:
1. When the ROM_MODE PMBus command is issued.
2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters
to a programmed device with no PMBus interaction.
3. When an invalid address is detected at power-up. By shorting one of the address pins to ground, an invalid
address can be generated that enables JTAG.
Internally, the circuits in the UCD92XX require 3.3V to operate. This can be provided directly on the V33x pins, or
it can be generated from the power supply input voltage using an internal series regulator and an external
transistor. The requirements for the external transistor are that it be an NPN device with a beta of at least 40.
Figure 3 shows the typical application using the external series pass transistor. The base of the transistor is
driven by a 10k Ω resistor to Vin and a transconduction amplifier whose output is on the VD33FB pin. The NPN
emitter becomes the 3.3 V supply for the chip and requires a bypass capacitor of 4 to 5 µ F.
Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a
0.1 to 1 µ F bypass capacitor from BPCap to ground.
Figure 5. Series-Pass 3.3V Regulator Controller I/O
The UCD9240 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the
POR circuit detects the V33D rise. When V33D is greater than VRESET, the device initiates the UVLO or
startup-delay sequence. At the end of the delay sequence, the device begins normal operation, as defined by the
downloaded device PMBus configuration.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCD9240