Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ELECTRICAL SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ADC MONITORING INTERVALS AND RESPONSE TIMES
- HARDWARE FAULT DETECTION LATENCY
- PMBus/SMBus/I2C
- I2C/SMBus/PMBus Timing Characteristics
- FUNCTIONAL OVERVIEW
- PMBus Interface
- Resistor Programmed PMBus Address Decode
- JTAG Interface
- Bias Supply Generator (Series Regulator Controller)
- Power On Reset
- External Reset
- Output Voltage Adjustment
- Analog Front End (AFE)
- Digital Compensator
- DPWM Engine
- Flexible Rail/Power Stage Configuration
- DPWM Phase Distribution
- DPWM Synchronization
- Phase Shedding at Light Current Load
- Phase Adding at Normal Current Load
- Output Current Measurment
- Output Current Balancing
- Overcurrent Detection
- Current Foldback Mode
- Input Voltage and Current Monitoring
- Temperature Monitoring
- Temperature Balancing
- Soft Start, Soft Stop Ramp Sequence
- Input UV Lockout
- Voltage Tracking
- Sequencing
- Fan Control
- Non-volatile Memory Error Correction Coding
- APPLICATION INFORMATION
External Reset
Output Voltage Adjustment
VOUT_MARGIN_HIGH
VOUT_CAL_OFFSET
VOUT_MARGIN_LOW
VOUT_COMMAND
+
Limiter
VOUT_
SCALE_
LOOP
“Reference
Voltage
Equivalent”
OPERATION
Command
VOUT_MAX
3:1
Mux
Analog Front End (AFE)
EApx
EAnx
6-bitresult
eADC
VrefDAC
CPU
PMBus
G
AFE
= 1, 2, 4 or 8
Vead
G
eADC
= 8mV/LSB
Vref = 1.563 mV/LSB
+
+
UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ...................................................................................................................................................
www.ti.com
The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low
voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a pull up resistor to
3.3V is recommended.
The nominal output voltage is programmed by a combination of PMBus commands: VOUT_COMMAND,
VOUT_CAL_OFFSET, and VOUT_MAX. Their relationship is shown in Figure 6 . Output voltage margining is
configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands. The OPERATION command
selects between the nominal output voltage and either of the margin voltages. The OPERATION command also
includes an option to suppress certain voltage faults and warnings while operating at the margin settings.
Figure 6. PMBus Voltage Adjustment Methods
For a complete description of the commands supported by the UCD9240 see the UCD92xx PMBUS Command
Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™
Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands to
configure the UCD9240 device.
Figure 7. Analog Front End Block Diagram
The UCD9240 senses the power supply output voltage differentially through the EAP and EAN pins. The error
amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage
sense signals. The fully differential nature of the error amplifier also ensures low offset performance.
The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus
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Product Folder Link(s): UCD9240