Datasheet

EAp
EAn
V
OUT
R
1
R
IN
I
OFF
R
2
2 1 2
1 2 1 2
1 2 1 2
= +
æ ö æ ö
+ + + +
ç ÷ ç ÷
è ø è ø
EA OUT OFF
IN IN
R R R
V V I
R R R R
R R R R
R R
1
2
1
1
1
=
æ ö
- + ±
ç ÷
è ø
EA
OUT EA OFF
IN
R V
R
R
V V R I
R
Digital Compensator
UCD9240
www.ti.com ................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then
transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by
the Vref DAC as shown in Figure 7 . The resulting error voltage is then amplified by a programmable gain circuit
before the error voltage is converted to a digital value by the flash ADC. This programmable gain is configured
through the PMBus and affects the dynamic range and resolution of the sensed error voltage as shown in
Table 3 .
Table 3. Analog Front End Resolution
AFE_GAIN for PMBus EFFECTIVE ADC
AFE GAIN DIGITAL ERROR VOLTAGE DYNAMIC RANGE (mV)
COMMAND RESOLUTION (mV)
1 0 8 -256 to 248
2 1 4 -128 to 124
4 2 2 -64 to 62
8 3 1 -32 to 31
The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by
issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank
for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This
allows the user to trade-off resolution and dynamic range for each operational mode.
The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.
However, its range is limited as shown in Table 3 . If the output voltage is different from the reference by more
than this, the EADC reports a saturated value at -32 LSBs or 31 LSBs. The UCD9240 overcomes this limitation
by adjusting the setpoint DAC up or down in order to bring the error voltage out of saturation. In this way, the
effective range of the ADC is extended. When the EADC saturates, the setpoint DAC is slewed at a rate of 0.156
V/ms, referred to the EA differential inputs.
Figure 8. Input Offset Equivalent Circuit
To obtain the best possible accuracy, the input resistance and offset current on the device should be considered
when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the
UCD9240. The input resistance and input offset current are specified in the parametric tables in this datasheet.
The effect of the offset current can be reduced by making the resistance of the divider network low. R1 should be
between 1k Ω and 5k Ω . Then R2, the lower divider resistor, can be calculated as:
Each voltage rail controller in the UCD9240 includes a digital compensator. The compensator consists of a
nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter
section cascaded with a first order IIR filter section.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): UCD9240