Datasheet

Nonlinear Gain Block
Threshold
logic
Gain 0
Gain 1
Gain 2
Gain 3
Gain 4
eADC
Limit 0
Limit 3
Limit 2
Limit 1
z
-1
+
X
X
B01
z
-1
X
B11
X
B21
+
Clamp z
-1
z
-1
X
X
+
A11 A21
z
-1
X
+
B12
z
-1
Clamp
X
A21
2nd Order Filter Section
1st Order Filter Section
Duty out
DPWM Engine
UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................... www.ti.com
The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the
compensator coefficients. The design tool allows the compensator to be described in terms of the pole
frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™
Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based
on the total loop gain for each feedback system. The coefficients of the filter sections are generated through
modeling the power stage and load.
Additionally, the UCD9240 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or
tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is
below the configured light load threshold.
The compensator also allows the minimum and maximum duty cycle to be programmed. This again is done by
issuing a PMBus command to the device.
Figure 9. Digital Compensator
The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from
zero. Typically Limit 0 and Limit 1 would be configured with negative values between -1 and -32 and Limit 2 and
Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to
be symmetric. For example, the four limit registers could all be set to positive values causing the Gain 0 value to
set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.
The cascaded 1st order filter section is used to generated the third zero and third pole.
The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse
width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty
cycle as a digital number representing a value from 0 to 1 This duty cycle value is multiplied by the configured
period to generate a comparator threshold value. This threshold is compared against the high speed switching
period counter to generate the desired DPWM pulse width. This is shown in Figure 10 . The resolution of the duty
period is nominally 250 picoseconds.
Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the
SYNC_IN and SYNC_OUT pins. Configuration of the synchronization function is done through a MFR_SPECIFIC
PMBus command. See the DPWM Synchronization section for more details.
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Product Folder Link(s): UCD9240