Datasheet

high
res
ramp
counter
Clk
reset
Switchperiod
Currentbalanceadj
Compensatoroutput
(calculateddutycycle)
EADCtrigger
threshold
PWMgatedrive
output
SysClk
SyncIn
EADC
trigger
SyncOut
S
R
DPWMEngine(1of4)
Flexible Rail/Power Stage Configuration
DPWM Phase Distribution
3
13
=
rail-rail spread SW
t t
UCD9240
www.ti.com ................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
Figure 10. DPWM Engine
The switching frequency is set by issuing the FREQUENCY_SWITCH PMBus command.
The UCD9240 can control up to four rails, each of which can comprise a programmable number of power stages.
Constraints on the mapping of power stages to rails are described in detail in the UCD92xx PMBus Command
Reference under the PHASE_INFO command.
While there is significant flexibility in terms of mapping power stages to output rails, the differential voltage
feedback signals (EAP/EAN) cannot be re-mapped through any commands, and therefore, must be connected to
the proper input on the circuit board. Because the EADC sample trigger for a given front end stage is derived
from the ramp timer of the first (lowest numbered) DPWM on the rail, the system must ensure that the number of
the EADC and the number of the first DPWM match. For example, consider a two rail configuration in which 4
power stages (1A, 2A, 1B and 2B) are assigned to the first rail and 2 power stages (3A and 4A) to the second.
The first DPWM on the first rail is 1; its voltage feedback must be through EAP1/EAN1. The first DPWM on the
second rail is 3; its voltage feedback must be through EAP3/EAN3. (In this configuration EAP2/EAN2 and
EAP4/EAN4 are unused and are disabled to reduce unnecessary power consumption.)
The number of voltage rails is configured using the PHASE_INFO PMBus command. The UCD9240
automatically synchronizes the first power stage of each voltage rail. The phase (in time) of each 1st power stage
is shifted by an amount in order to minimize input current ripple. The amount that each 1st power stage is shifted
is:
Where t
SW
is the period of the rail with the fastest switching frequency.
The ratio 3/13 is chosen because it is close to 1/4, but it is a prime ratio. This should ensure that any
configuration of rails and power stages should not have the leading edge of the DPWM signal aligned.
The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage
rail. When multiple power stages are configured to drive a voltage rail, the UCD9240 automatically distributes the
phase of each DPWM output to minimize ripple. This is accomplished by setting the rising edge of each DPWM
pulse to be separated by:
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