Datasheet

=
SW
phase-phase spread
Phases
t
t
N
DPWM Synchronization
Phase Shedding at Light Current Load
Phase Adding at Normal Current Load
Output Current Measurment
UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................... www.ti.com
Where t
SW
is the switching period and N
Phases
is the number of power stages driving a voltage rail.
DPWM synchronization provides a method to link the timing between rails on two distinct devices at the switching
rate; i.e., two rails on different devices can be configured to run at the same frequency and sync forcing them not
to drift from each other. (Note that within a single device, because all rails are driven off a common clock there is
no need for an internal sync because rails wont drift.)
The PMBus SYNC_IN_OUT command sets which rails (if any) should follow the sync input, and which rail (if
any) should drive the sync output.
For rails that are following the sync input, the DPWM ramp timer for that output is reset when the sync input goes
high. This allows the slave device to sync to inputs that are either faster or slower than it is. On the fast side,
there is no limit to how much faster the input is compared to the defined frequency of the rail; when the pulse
comes in, the timer is reset and the frequencies are locked. This is the standard mode of operation - setting the
slave to run slower, and letting the sync speed it up.
If the slave rail is running fast, the sync pulse resets the counter after the DPWM output has already been turned
on. Resetting the counter at this point results in a larger duty cycle for that period. Because the system is closed
loop; however, the controller reacts by decreasing the commanded control effort, with the result being a
regulated rail synchronized to a slower master. Synchronizing to the slower master does have a limit however. If
the master is slow enough that the DPWM output has sufficient time to output the entire command pulse before
the sync input arrives, the result is a double pulse. This is likely an undesirable mode of operation.
The Sync Input and Output Configuration Word set by the PMBus command consists of two bytes. The upper
byte (sync_out) controls which rail drives the sync output signal (0=DWPM1, 1=DPWM2, 2=DPWM3, 3=DPWM4.
Any other value disables sync_out). The lower byte (sync_in) determines which rail(s) respond to the sync input
signal (each bit represents one rail - note that multiple rails can be synchronized to the input). The DPWM period
is aligned to the sync input. For more information, see the UCD92xx PMBUS Command Reference.
Note that once a rail is synchronized to an external source, the rail-to-rail spacing that attempts to minimize input
current ripple are lost. Rail-to-rail spacing can only be restored by power cycling or issuing a SOFT_RESET
command.
By issuing LIGHT_LOAD_LIMIT_LOW, LIGHT_LOAD_LIMIT_HIGH, and LIGHT_LOAD_CONFIG commands, the
UCD9240 can be configured to shed (disable) power stages when at light load. When this feature is enabled, the
device disables the configured number of power stages when the average current drops below the specified
LIGHT_LOAD_LIMIT_LOW. In addition, a separate set of compensation coefficients can be loaded into the
digital compensator when entering a light load condition.
After shedding phases, if the current load is increased past the LIGHT_LOAD_LIMIT_HIGH threshold, all phases
are re-enabled. If the compensator was configured for light load, the normal load coefficients are restored as
well. See the UCD92xx PMBUS Command Reference for more information.
Pins CS-1A, CS-1B, CS-2A, CS-2B, CS-3A, CS-3B, CS-4A, and CS-4B are used to measure either output
current or inductor current in each of the controlled power stages. PMBus commands IOUT_CAL_GAIN and
IOUT_CAL_OFFSET are used to calibrate each measurement. See the UCD92xx PMBus Command Reference
for specifics on configuring this voltage to current conversion.
When the measured current is outside the range of either the overcurrent or undercurrent threshold, a FAULT is
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