Datasheet

Temperature Balancing
Soft Start, Soft Stop Ramp Sequence
2 4 6 8 10 14 16120
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
Time ms
Startintoapre-bias
Startfromzero
2 4 6 8 10 14 16120
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
Time ms
Bridged, 0.45-Vbias
Unbridged,
nobias
Unbridged,
0.45-Vbias
Soft-Start Soft-Stop
V
olts
Volts
PWMbeginsherefrom0outputvoltage
PWMbeginsherewithpre-bias
UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................... www.ti.com
Table 5. Temperature Sensor Mapping (continued)
TEMPERATURE MUX INPUT POWER STAGE RAIL
A4 PWM-2B Rail-2B
A5 PWM-4A Rail-2C
A6 - -
A7 - -
Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a
larger share of the current. Temperature balancing occurs slowly (the loop runs at a 10 Hz rate), and only when
the phase currents exceeds the PMBus settable TEMP_BALANCE_IMIN. This minimum current threshold
prevents the controller from "winding up" and forcing one phase to carry all the current under a low-load
condition, when the total current may be insufficient to significantly affect phase temperatures.
The UCD9240 performs soft start and soft stop ramps under closed loop control. Performing a start or stop ramp
or tracking is considered a separate operational mode. The other operational modes are normal regulation and
light load regulation. Each operational mode can be configured to have an independent loop gain and
compensation. Each set of loop gain coefficients is called a "bank" and is configured using the CLA_GAINS
PMBus command.
Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal
reference toward the commanded reference voltage at the rate specified by the TON_DELAY time. The DPWM
and SRE outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the
output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE. This
ensures that a constant ramp rate is maintained, and that the ramp is completed at the same time it would be if
there was not a pre-bias condition.
The operation of soft-stop ramps depends on how the voltage rail is configured. If PAGE_ISOLATED is set to 1
through the PAGE_ISOLATED PMBus command, the controller assumes that it is the only device driving the
voltage rail, and the soft-stop ramp is performed with SRE enabled until the voltage associated with the
configured minimum supported pulse width is reached. If PAGE_ISOLATED is set to 0, the controller assumes
that multiple power stages may be supplying the voltage rail and SRE is disabled at the beginning of the
soft-stop ramp. Figure 13 shows the operation of soft-start ramps and soft-stop ramps.
Figure 13. Start and Stop Ramps
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