Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ELECTRICAL SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ADC MONITORING INTERVALS AND RESPONSE TIMES
- HARDWARE FAULT DETECTION LATENCY
- PMBus/SMBus/I2C
- I2C/SMBus/PMBus Timing Characteristics
- FUNCTIONAL OVERVIEW
- PMBus Interface
- Resistor Programmed PMBus Address Decode
- JTAG Interface
- Bias Supply Generator (Series Regulator Controller)
- Power On Reset
- External Reset
- Output Voltage Adjustment
- Analog Front End (AFE)
- Digital Compensator
- DPWM Engine
- Flexible Rail/Power Stage Configuration
- DPWM Phase Distribution
- DPWM Synchronization
- Phase Shedding at Light Current Load
- Phase Adding at Normal Current Load
- Output Current Measurment
- Output Current Balancing
- Overcurrent Detection
- Current Foldback Mode
- Input Voltage and Current Monitoring
- Temperature Monitoring
- Temperature Balancing
- Soft Start, Soft Stop Ramp Sequence
- Input UV Lockout
- Voltage Tracking
- Sequencing
- Fan Control
- Non-volatile Memory Error Correction Coding
- APPLICATION INFORMATION

Power Stage
Gplant(f)
Gdiv(f)
K
AFE
K
EADC
K
nonlinear
G
CLA2
G
CLA1
K
PWM
+
Vout
Vin
G
delay
V
ref
DAC
divider
UCD9240
CPU
PMBus
Automatic System Identification ( Auto-ID™)
EAp/EAn Voltage Sense Filtering
UCD9240
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................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
CONSTANT GAIN COMPONENTS DESCRIPTION
G
delay
Phase shift due to the delays in the control loop.
Knonlinear Nonlinear function gain. Gain for the limit interval that contains zero error.
G
CLA2
Transfer function of the second order filter section of the compensator.
G
CLA1
Transfer function of the first order filter section of the compensator.
K
PWM
Accounts for the bit resolution of the input to the DPWM
Figure 15. Loop Gain Contributions
Several of the gain blocks are programmable. They are configured by issuing a CLA_GAINS command over the
PMBus. The syntax for this command is shown in the UCD92xx PMBUS Command Reference. These gains can
also be configured using the Fusion Digital Power™ Designer PC program.
By using digital circuits to create the control function for a switch-mode power supply, additional features can be
implemented. One of those features is the measurement of the open loop gain and stability margin of the power
supply without the use of external test equipment. This capability is called automatic system identification or
Auto-ID™. To identify the frequency response, the UCD9240 internally synthesizes a sine wave signal and
injects it into the loop at the set point DAC. This signal excites the system, and the closed-loop response to that
excitation can be measured at another point in the loop. The UCD9240 measures the response to the excitation
at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is
calculated. The open-loop transfer function may be calculated from the closed-loop response.
Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be
divided out of the measured open-loop gain. In this way the UCD9240 can accurately measure the power
stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and
send the measurement data back to a host through the PMBus interface without the need for external test
equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus
Command Reference.
Conditioning should be provided on the EAp and EAn signals. Figure 16 shows a divider network between the
output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output
voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the
signal conditioned by the low-pass filter formed by R1 and C2.
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