Datasheet

Power Stage
Vout
divider
R
1
R
2
C
2
EAn
EAp
1 2
1 2
1 2
1
= = = =
- +
P P EA
P
OU T
R R V R R
R R where K and R
K K V R R
2
1
2 0.35p
=
´ ´ ´
SW P
C
F R
Current Sense Input FIltering
Output Voltage Margining
Calibration
Data Logging
UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................... www.ti.com
Figure 16. EAp/EAn Input Network
As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly
across an output capacitor, and route the positive and negative differential sense signals as a balanced pair of
traces or as a twisted pair cable back to the controller. Put the divider network close to the controller. This
ensures that there is a low impedance driving the differential voltage sense signal from the voltage rail output
back to the controller. The resistance of the divider network is a trade-off between power loss and minimizing
interference susceptibility. A parallel resistance of 1k to 4k Ω is a good compromise.
It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an
additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter,
the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:
Each power stage current is monitored by the device at the CS pins. There are 4 "A" channel pins and 2 or 4 "B"
channel pins (64 or 80 pin package). The B channels monitor the current with a 12-bit ADC and samples each
current sense voltage in turn. The A channels monitor the current with the same12-bit ADC and also monitor the
current with a digitally programmable analog comparator.
Because the current sense signal is digitally sampled, it should be conditioned with an RC network acting as an
anti-alias filter. Since the sample rate for the CS inputs is 1/ TIout, a good cutoff frequency for the RC network is
from 2 kHz to 3 kHz.
The UCD9240 supports Voltage Margining using the PMBus VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW
commands in conjunction with the OPERATION command. The margin voltages can be configured at device
configuration and saved into Data Flash. The output can be commanded to switch between Margin High,
Nominal, and Margin Low using bits [3:2] of the OPERATION command.
To optimize the operation of the UCD9240, PMBus commands are supplied to enable fine calibration of output
voltage, output current, and temperature measurements. The supported commands and related calibration
formulas may be found in the UCD92xx PMBUS Command Reference.
The UCD9240 maintains a data log in non-volatile memory. This log tracks the peak internal and external
temperature measurements, peak current measurements, and fault history. The PMBus commands and data
format for data logging can be found in the UCD92xx PMBUS Command Reference (SLUU337 )
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