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UCD9244

www.ti.com

SLVSAL6A –NOVEMBER 2010–REVISED FEBRUARY 2011

Digital PWM System Controller with 4-bit, 6-bit, or 8-bit VID Support

Check for Samples: UCD9244

FEATURES

APPLICATIONS

• Networking Equipment

• Fully Configurable Four-Output Non-Isolated

DC/DC PWM Controller with support for

• Telecommunications Equipment

TMS320C6670™ and TMS320C6678™ DSP VID

• FPGA, DSP, and Memory Power

interface

DESCRIPTION

• Supports Switching Frequencies Up to 2MHz

With 250 ps Duty-Cycle Resolution

The UCD9244 is a four-rail synchronous buck digital

• Up To 1mV Closed Loop Resolution

PWM controller designed for non-isolated DC/DC

power applications. This device integrates dedicated

• Hardware-Accelerated, 3-Pole/3-Zero

circuitry for DC/DC loop management with support for

Compensator with Non-Linear Gain for

up to four VID interfaces. Additionally, the UCD9244

Improved Transient Performance

has flash memory and a serial interface to support

• Supports Multiple Soft-Start and Soft-Stop

configurability, monitoring and management.

Configurations Including Prebias Start-up

Several Voltage Identification (VID) modes are

• Supports Voltage Margining and Sequencing

supported, including a 4-bit parallel interface, a 6-bit

• Sync In Pin Aligns DPWM Clocks Between

interface and an 8-bit serial interface.

Multiple UCD92xx Devices

The UCD9244 was designed to provide a wide

• 12-Bit Digital Monitoring of Power Supply

variety of desirable features for non-isolated DC/DC

Parameters Including:

converter applications while minimizing the total

system component count by reducing external

– Input Current and Voltage

circuits. The solution integrates multi-loop

– Output Current and Voltage

management with sequencing, margining and

– Temperature at Each Power Stage

tracking to optimize for total system efficiency.

Additionally, loop compensation and calibration are

– Auxiliary ADC Inputs

supported without the need to add external

• Multiple Levels of Over-current Fault

components.

Protection:

To facilitate configuring the device, the Texas

– External Current Fault Inputs

Instruments Fusion Digital Power™ Designer is

– Analog Comparators Monitor Current

provided. This PC based Graphical User Interface

Sense Voltage

offers an intuitive interface to the device. This tool

– Current Continually Digitally Monitored

allows the design engineer to configure the system

operating parameters for the application, store the

• Over and Under-voltage Fault Protection

configuration to on-chip non-volatile memory and

• Over-temperature Fault Protection

observe both frequency domain and time domain

• Enhanced Nonvolatile Memory With Error

simulations for each of the power stage outputs.

Correction Code (ECC)

TI has also developed multiple complementary power

• Device Operates From a Single Supply With an

stage solutions – from discrete drivers in the UCD7k

Internal Regulator Controller That Allows

family to fully tested power train modules in the PTD

Operation Over a Wide Supply Voltage Range

family. These solutions have been developed to

complement the UCD92xx family of system power

• Supported by Fusion Digital Power™

controllers.

Designer, a Full Featured PC Based Design

Tool to Simulate, Configure, and Monitor

Power Supply Performance.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320C6670, TMS320C6678, Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SUPPLY CURRENT IV33A V33A = 3.3 V 8 15 IV33DIO V33DIO = 3.3 V 2 10 V33D = 3.3 V 40 45 V33D = 3.3 V storing configuration parameters in flash memory 50 55 3.3 3.6 4 4.6 0.4 8 IV33D Supply current IV33D mA INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS V33 3.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Dgnd +0.25 V DIGITAL INPUTS/OUTPUTS VOL Low-level output voltage IOL = 6 mA (1), V33DIO = 3 V VOH High-level output voltage IOH = -6 mA (2), V33DIO = 3 V VIH High-level input voltage V33DIO = 3V VIL Low-level input voltage V33DIO = 3.5 V V33DIO –0.6V 2.1 V 3.6 V 1.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage and output current, plus six other variables (input voltage, internal temperature, and four external temperature sensors). The length of the sequence is determined by the number of output rails (NumRails) configured for use.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com HARDWARE FAULT DETECTION LATENCY The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer. PARAMETER TEST CONDITIONS tFAULT Time to disable DPWM output base on active FAULT pin signal tCLF Time to disable the DPWM A output based on internal analog comparator MAX TIME UNIT High level on FAULT pin 18 µs Step change in CS voltage from 0V to 2.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 CS4A 1 CS3A 2 CS2A 3 VinMon Agn d3 Temp 4/ Au x ADC4 Tem p3/ Au x AD C3 Addr 0 Ad dr 1 CS1A V 33FB E An 4 E Ap4 E An 3 E Ap3 E An 2 E Ap2 E An 1 E Ap1 Agn d 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 www.ti.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 1.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 1.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL APPLICATION SCHEMATIC Figure 3 shows the UCD9244 power supply controller as part of a system that provides the regulation of two independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate drivers for each power stage.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL OVERVIEW The UCD9244 contains four Fusion Power Peripherals (FPP). Each FPP consists of: • A differential input error voltage amplifier. • A 10-bit DAC used to set the output regulation reference voltage. • A fast ADC with programmable input gain to digitally measure the error voltage.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 2. PMBus Address Bins (1) ADDR1 ADDR0 (1) (2) (3) (short) < 36.5k 42.2k 48.7k 56.2k 64.9k 75k 86.6k 100k 115k 133k 154k 178k 205k (open) > 237k < 36.5k (short) 126 126 126 126 126 126 126 126 126 126 126 126 126 126 42.2k 126 126 (2) 1 2 3 4 5 6 7 8 9 10 11 (3) 126 48.7k 126 126 (2) 13 14 15 16 17 18 19 20 21 22 33 126 56.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Regardless of which VID mode is used, the commanded output voltage reference is set according to this formula: Vref_cmd = (VID_CODE × VID_Slope) + VID_Offset, where VID_Slope = (VID_Vout_High – VID_Vout_Low) / ((2^VID_Format) -1), and VID_Offset = VID_Vout_Low. The VID_Vout_High, VID_Vout_Low, and VID_Format values are set using the VID_CONFIG PMBus command.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com The falling edge of the VID_S line triggers the UCD9244 to read bits 2:0 on the three VID data lines. The rising edge of VID_S triggers the UCD9244 to read bits 5:3 on the three VID data lines and calculate a new VOUT setpoint. This calculation takes from 35 to 135µs. The output voltage will then slew to the new setpoint voltage at the rate specified by the VOUT_TRANSITION_RATE PMBus command.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. 6-bit VID Timing SYMBO L PARAMETER MIN TYP MAX UNITS Tr Data and clock rise time – 2.5 µs Tf Data and clock fall time – 0.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com VOUT TMSGVO TMSG Addr Cmd TVO Data PEC Start Stop PMBus Clock ACK ACK ACK ACK PMBus Data Figure 8. PMBus Timing for VID_CODE_RAILn Command Table 4.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Bias Supply Generator (Shunt Regulator Controller) The I/O and analog circuits in the UCD9244 require 3.3V to operate. This can be provided using a stand-alone external 3.3V supply, or it can be generated from the main input supply using an internal shunt regulator and an external transistor. Regardless of which method is used to generate the 3.3V supply, bypass capacitors of 0.1 µF and 4.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ON_OFF_CONFIG The ON_OFF_CONFIG command is used to select the method of turning rails on and off. It can be configured so that the rail: • stays off, • turns on automatically, • responds to the PMBus_Cntrl pin, • responds to OPERATION command, or • responds to logical-AND of the PMBus_Cntrl pin and the OPERATION command. The ON_OFF_CONFIG command also sets the active polarity of the PMBus_Cntrl pin.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Analog Front End (AFE) VEAP VEA GAFE = 1, 2, 4, or 8 VEAN Vead Error ADC 6-bit result G eADC = 8mV/LSB Vref DAC CPU Vref = 1.563 mV/LSB PMBus Figure 11. Analog Front End Block Diagram The UCD9244 senses the power supply output voltage differentially through the EAP and EAN pins. The error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage sense signals.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Voltage Sense Filtering Conditioning should be provided on the EAP and EAN signals. Figure 12 shows a divider network between the output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the signal conditioned by the low-pass filter formed by R1 and C2.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Figure 13. Digital Compensator To calculate the values of the digital compensation filter continuous-time design parameters KDC, FZ ands QZ are entered into the Fusion Digital Power Designer software (or it calculates them automatically). Where the compensating filter transfer function is H (s ) = K DC S2 s + +1 2 wZ wZQZ æ s ö sç + 1÷ è wP2 ø (5) There are approximate limits the design parameters KDC, FZ ands QZ.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com DPWM Engine The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the configured period to generate a comparator threshold value.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com DPWM Phase Synchronization DPWM synchronization provides a method to link the timing between voltage rails controlled by the UCD92xx device--either internally or between devices. The configuration of the synchronization between rails is performed by the issuing the SYNC_CONFIG command. For details of issuing this command, see the UCD92xx PMBUS Command Reference (SLUU337).
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ADC sample = Period-EADC trigger Early sync Sync-in EADC Threshold Convert ADC sample and calculate compensated error insufficient time to convert ADC sample Compensated error previous control effort PWM pulse Figure 15. Relationship of EADC Trigger to external Sync If two rails share a common sync source other than the SyncIn pin, they must have the same delay.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 R = 0.45 Nrails TIout C www.ti.com (7) where Nrails is the number of rails configured and TIout is the sample period for the current sense inputs. Therefore, when the comparator is not used, the recommended component values for the RC network are C = 10 nF and R = 35.7 kΩ.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com The worst case response time to an over-current condition is the sum of the sampling interval (Table 8) and the smoothing filter lag, tlag from Equation 11. Current Foldback Mode When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the UCD9244 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by IOUT_OC_FAULT_LIMIT.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal reference toward the commanded reference voltage at the rate specified by the TON_RISE time and VOUT_COMMAND. The DPWM outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Non-volatile Memory Error Correction Coding The UCD9244 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION Automatic System Identification ( Auto-ID™) By using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. One of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. This capability is called automatic system identification or Auto-ID™.
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UCD9244 SLVSAL6A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY Note: Page numbers of current version may differ from previous versions. Changes from Original (November 2010) to Revision A Page • Added "4-bit, 6-bit, or 8-bit VID Support" to Title line ........................................................................................................... 1 • Added TI DSP device numbers to 1st Feature bullet .....................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD9244RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD9244RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD9244RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD9244RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD9244RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD9244RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD9244RGCT VQFN RGC 64 250 210.0 185.0 35.
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