Datasheet

UCD9246
www.ti.com SLVSA34 –JANUARY 2010
Table 1. PMBus Address Bins (continued)
R
PMBus
PMBus RESISTANCE
PMBus ADDRESS
(kΩ)
6 100
5 86.6
4 75
3 64.9
2 56.2
1 48.7
0 42.2
short –
A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the
PMBus address to default to address 126. A high impedance (open) on either address pin that produces a
voltage above the maximum voltage also causes the PMBus address to default to address 126.
Some addresses should be avoided, see Table 2
Table 2. PMBus Address Assignment Rules
ADDRESS STATUS REASON
0 Prohibited SMBus generall address call
1-10 Avaliable
11 Avoid Causes confilcts with other devices during program flash updates.
12 Prohibited PMBus alert response protocol
13–125 Avaliable
126 Avoid Default value; may cause conflicts with other devices.
127 Prohibited Used by TI manufacturing for device tests.
JTAG Interface
The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in
order to enable the SEQ-1 sequencing pin, sync, and power good status pins with which it is multiplexed. There
are three conditions under which the JTAG interface is enabled:
1. When the ROM_MODE PMBus command is issued.
2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters
to a programmed device with no PMBus interaction.
3. When an invalid address is detected at power-up. By shorting one of the address pins to ground, an invalid
address can be generated that enables JTAG.
Bias Supply Generator (Shunt Regulator Controller)
Internally, the circuits in the UCD9246 require 3.3V to operate. This can be provided directly on the V33x pins, or
it can be generated from the power supply input voltage using an internal shunt regulator and an external
transistor. The requirements for the external transistor are that it be an NPN device with a beta of at least 40.
Figure 6 shows the typical application using the external series pass transistor. The base of the transistor is
driven by a 10kΩ resistor to Vin and a transconduction amplifier whose output is on the VD33FB pin. The NPN
emitter becomes the 3.3V supply for the chip and requires bypass capacitors of 0.1µF and 4.7µF.
The transconductance amplifier sinks current into the V33FB pin, in order to regulate the amount of current
allowed into the base of the transistor, which regulates the collector current, which determines the emitter voltage
(3.3V). The resistor value should be sized low enough to give sufficient base drive at minimum input voltage, yet
large enough to not exceed the maximum current sink capability of the V33FB pin at maximum input voltage.
Higher beta transistors help in increasing the minimum resistance value, as less base current is needed to
sufficiently drive the higher beta transistor. A resistor value of 10 kOhms works well for most applications that
use the FCX491A BJT.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13