Datasheet
UCD9246
16
14
15
13
12
11
3
2
4
10
9
8
7
5
1
6
33
35
34
36
37
38
46
47
45
39
40
41
42
44
48
43
32
30
31
29
28
27
19
18
20
26
25
24
23
21
17
22
49
51
50
52
53
54
62
63
61
55
56
57
58
60
64
59
CS-4A
CS-3A
CS-2A
Vin/ Iin
Vtrack
Temperature
V33DIO
DGND1
SRE-1B
SRE-1A
nRESET
TRCK
FLT-1A
FLT-1B
FLT-2A
FLT-2B
PMBus_Clock
PMBus_Data
DPWM-1A
DPWM-1B
DPWM-2A
DPWM-2B
DPWM-3A
DPWM-4A
FLT-3A
SRE-4A
DGND2
PMBus_Alert
SRE-2B
SRE-3A
TMUX-0
TMUX-1
FLT-4A
TCK/SEQ-1
TDO/Sync_out
TDI /Sync_in
TMS/PGood
nTRST
SRE-2A
SEQ-2
TMUX-2
DGND3
V33DIO
V33D
V33A
BPCap
AGND1
AGND2
EAP1
EAN1
EAP2
EAN2
EAP3
EAN3
EAN4
EAP4
V33FB
CS-1A
CS-2B
CS-1B
AGND3
ADDR-0
ADDR-1
PMBus_Cntl
UCD9246
SLVSA34 –JANUARY 2010
www.ti.com
The UCD9246 is available in an 64-pin QFN package (RGC).
Figure 3. Pin Assignment Diagram
TYPICAL APPLICATION SCHEMATIC
Figure 4 shows the UCD9246 power supply controller as part of a system that provides the regulation of one
six-phase power supply. The loop for the power supply is created by the voltage output feeding into the
differential voltage error ADC (EADC) input, and completed by DPWM outputs feeding into the gate drivers for
each power stage.
The ±V
sense
rail signal must be routed to the EAp/EAn input that matches the number of the lowest DPWM
configured as part of the rail. (See more detail in Flexible Rail/Power Stage Configuration.)
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