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UCD9248

www.ti.com

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

Digital PWM System Controller

FEATURES

APPLICATIONS

• Fully Configurable Multi-Output and Multi-

• Industrial/ATE

Phase Non-Isolated DC/DC PWM Controller

• Networking Equipment

• Controls Up to 4 Voltage Rails and Up to 8

• Telecommunications Equipment

Phases

• Servers

• Supports Switching Frequencies Up to 2MHz

• Storage Systems

with 250 ps Duty-Cycle Resolution

• FPGA, DSP and Memory Power

• Up To 1mV Closed Loop Resolution

• Hardware-Accelerated, 3-Pole/3-Zero

DESCRIPTION

Compensator with Non-Linear Gain for

The UCD9248 is a multi-rail, multi-phase

Improved Transient Performance

synchronous buck digital PWM controller designed for

non-isolated DC/DC power applications. This device

• Supports Multiple Soft-Start and Soft-Stop

integrates dedicated circuitry for DC/DC loop

Configurations Including Prebias Start-up

management with flash memory and a serial interface

• Supports Voltage Tracking, Margining and

to support configurability, monitoring and

Sequencing

management.

• Supports Current and Temperature Balancing

The UCD9248 was designed to provide a wide

for Multi-Phase Power Stages

variety of desirable features for non-isolated DC/DC

• Supports Phase Adding/Shedding for Multi-

converter applications while minimizing the total

Phase Power Stages

system component count by reducing external

circuits. The solution integrates multi-loop

• Sync In/Out Pins Align DPWM Clocks Between

management with sequencing, margining, tracking

Multiple UCD92xx Devices

and intelligent phase management to optimize for

• 12-Bit Digital Monitoring of Power Supply

total system efficiency. Additionally, loop

Parameters Including:

compensation and calibration are supported without

– Input/Output Current and Voltage

the need to add external components.

– Temperature at Each Power Stage

To facilitate configuring the device, the Texas

• Multiple Levels of Over-current Fault

Instruments Fusion Digital Power™ Designer is

provided. This PC based Graphical User Interface

Protection:

offers an intuitive interface to the device. This tool

– External Current Fault Inputs

allows the design engineer to configure the system

– Analog Comparators Monitor Current

operating parameters for the application, store the

Sense Voltage

configuration to on-chip non-volatile memory and

observe both frequency domain and time domain

– Current Continually Digitally Monitored

simulations for each of the power stage outputs.

• Over- and Under-voltage Fault Protection

TI has also developed multiple complementary power

• Over-temperature Fault Protection

stage solutions – from discrete drivers in the UCD7k

• Enhanced Nonvolatile Memory with Error

family to fully tested power train modules in the PTD

Correction Code (ECC)

family. These solutions have been developed to

• Device Operates From a Single Supply with an

complement the UCD9k family of system power

Internal Regulator Controller That Allows

controllers.

Operation Over a Wide Supply Voltage Range

• Supported by Fusion Digital Power™

Designer, a Full Featured PC Based Design

Tool to Simulate, Configure, and Monitor

Power Supply Performance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
UCD9248 www.ti.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER INPUTS EAPn, EANn VCM Common mode voltage each pin VERROR Internal error voltage range AFE_GAIN field of CLA_GAINS = 0 (1) –0.15 1.848 –256 248 mV EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_GAINS= 3 REA Input Impedance Ground reference 0.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power stage's output current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 HARDWARE FAULT DETECTION LATENCY The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer. PARAMETER tFAULT tCLF TEST CONDITIONS MAX UNIT 15 + 3 × NumPhases µs Step change in CS voltage from 0V to 2.5V 4 Switch Cycles Step change in CS voltage from 0V to 2.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Figure 1.
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UCD9248 www.ti.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com AGND3 CS-1B CS-2B ADDR-0 ADDR-1 CS-1A CS-3B CS-4B Aux-in (AD14) Aux-in (AD13) V33FB EAn4 EAp4 EAn3 EAp3 EAn2 EAp2 EAn1 EAp1 AGND2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 The UCD9248 is available in an 80-pin TQFP package (PFC).
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 UCD7231 Power Stage Vin Vin Vin +3.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com PIN DESCRIPTIONS PIN NO. 10 PIN NAME DESCRIPTION 1 ADCref ADC Decoupling capacitor – tie 0.
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UCD9248 www.ti.com PIN NO. SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 PIN NAME DESCRIPTION 48 nTRST JTAG Test reset – tie to ground with 10kOhm resistor 49 PGood Power Good indication, Active high open-drain output. Pull-up to 3.3V with 10 kΩ resistor.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com FUNCTIONAL OVERVIEW The UCD9248 contains four fusion power peripherals (FPP). Each FPP can be configured to regulated up to four DC/DC converter outputs. There are eight PWM outputs that can be assigned to drive the converter outputs. Each FPP consists of: • A differential input error voltage amplifier • A 10-bit DAC used to set the output regulation reference voltage.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Table 1. PMBus Address Bins (continued) PMBus ADDRESS RPMBus PMBus RESISTANCE (kΩ) 5 86.6 4 75 3 64.9 2 56.2 1 48.7 0 42.2 short – A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the PMBus address to default to address 126.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com To Power Stage Vin FCX491A +3.3 V 4.7 mF 10 kW +1.8 V 0.1 mF V33A V33D BPCap V33FB 0.1 mF UC9248 Figure 6. Series-Pass 3.3V Regulator Controller I/O Power On Reset The UCD9248 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the POR circuit detects the V33D rise. When V33D is greater than VRESET, the device initiates an internal startup sequence.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 OPERATION Command VOUT_MAX VOUT_MARGIN_HIGH + 3:1 Mux VOUT_COMMAND VOUT_ SCALE_ LOOP Limiter Vref DAC VOUT_MARGIN_LOW VOUT_CAL_OFFSET Figure 7. PMBus Voltage Adjustment Methods For a complete description of the commands supported by the UCD9248 see the UCD92xx PMBUS Command Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™ Designer program.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Table 3. Analog Front End Resolution (continued) AFE_GAIN for PMBus COMMAND AFE GAIN EFFECTIVE ADC RESOLUTION (mV) DIGITAL ERROR VOLTAGE DYNAMIC RANGE (mV) 1 2 4 –128 to 124 2 4 2 –64 to 62 3 8 1 –32 to 31 The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the CLA_GAINS PMBus command.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Where K= VEA VOUT @ VOUT_SCALE_LOOP (3) It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter, the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as: 1 C2 = 2 p ´ 0.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Figure 10. Digital Compensation The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to be symmetric.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 DPWM Engine (1 of 4) SysClk SyncIn Clk high res ramp counter reset S Switch period R PWM gate drive output Current balance adj Compensator output EADC trigger (Calculated duty cycle) EADC trigger SyncOut threshold Figure 11. DPWM Engine Flexible Rail/Power Stage Configuration The UCD9248 can control up to four rails, each of which can comprise a programmable number of power stages.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage rail. When multiple power stages are configured to drive a voltage rail, the UCD9248 automatically distributes the phase of each DPWM output to minimize ripple.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Table 4. Output Current Filter Time Constants NUMBER OF OUTPUT RAILS OUTPUT CURRENT SAMPLING INTERVALS (µs) FILTER TIME CONSTANTS (ms) 1 200 0.7 2 400 1.4 3 600 2.1 4 800 2.8 For example, with a single rail, the filter has the transfer function characteristics that shows the signal magnitude at the output of the averaging filter due to a sine wave input for a range of frequencies.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Output Current Balancing When the UCD9248 is configured to drive multiple power stage circuits from one compensator, current balancing is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the connected power stage sections.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Current Foldback Mode When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the UCD9248 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com +3.3 V Vcc Temperature Temp _1A Temp _1B A0 Temp _2A Temp _2B A2 A3 Temp _3A A7 Temp _3B A5 S2 TMUX-2 Temp _4A A6 S1 TMUX-1 Temp _4B A7 S0 TMUX-0 A A1 CD74HC4051 Vee Gnd E Figure 12. Temperature Mux (1 rail, 8 phases) Below is an example of a system with two output voltage rails driven by 3 power stages each. The first output voltage rail is driven with DPWM-1A, DPWM-1B and DPWM-3A.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Table 5. Temperature Sensor Mapping TEMPERATURE MUX INPUT POWER STAGE A0 DPWM-1A A1 DPWM-1B A2 DPWM-3A A3 DPWM-2A A4 DPWM-2B A5 DPWM-4A A6 n/c A7 n/c Temperature Balancing Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a larger share of the current.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to minimize the error voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a soft start ramp or a soft stop ramp, and programmable ramp times, TON_RISE and TOFF_FALL determine how long the ramp takes. These PMBus commands are defined in the UCD92xx PMBUS Command Reference. The parameters can also be configured using the Fusion Digital Power™ Designer GUI (see http://focus.ti.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com Each rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it turns on and reaches its power good threshold. If the programmable timeout is reached before the input pin state matches its defined logic level, the rail is shut down, and a status error posted. This feature could be used, for example, to ensure that an LDO on the board did turn on when the main system voltage came up.
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UCD9248 www.ti.com SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 APPLICATION INFORMATION Automatic System Identification ( Auto-ID™) By using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. One of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. This capability is called automatic system identification or Auto-ID™.
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UCD9248 SLVSA33A – JANUARY 2010 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Original (January 2010) to Revision A Page • Changed in the Pin Descriptions table for pins 30 and 31. ................................................................................................ 10 • Deleted PowerPad from the Pin Descriptions table. ...........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCD9248PFCR Package Package Pins Type Drawing TQFP PFC 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD9248PFCR TQFP PFC 80 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.