USBN9603,USBN9604 USBN9603 USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support Literature Number: SNOS528L
- May 1998 USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support General Description Outstanding Features The USBN9603/4 are integrated, USB Node controllers. Other than the reset mechanism for the clock generation circuit, these two devices are identical. All references to “the device” in this document refer to both devices, unless otherwise noted. The device provides enhanced DMA support with many automatic data handling features.
Full-speed USB node device ● Integrated USB transceiver ● Supports 24 MHz oscillator circuit with internal 48 MHz clock generation circuit ● Programmable clock generator ● Serial Interface Engine (SIE) consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification 1.0 and 1.
.0 5.0 CONNECTION DIAGRAMS ........................................................................................................ 6 1.2 DETAILED SIGNAL/PIN DESCRIPTIONS .................................................................................. 7 1.2.1 Power Supply ................................................................................................................ 7 1.2.2 Oscillator, Clock and Reset ...................................................................................
7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 Clock Configuration Register (CCONF)...................................................................... 31 Revision Identifier (RID) .............................................................................................. 31 Node Functional State Register (NFSR) ..................................................................... 32 Main Event Register (MAEV) ........................................................
7.3 REGISTER MAP ........................................................................................................................ 50 Device Characteristics ABSOLUTE MAXIMUM RATINGS ............................................................................................ 52 8.2 DC ELECTRICAL CHARACTERISTICS ................................................................................... 52 8.3 AC ELECTRICAL CHARACTERISTICS ..................................................................
2 D5 INTR 28-Pin CSP 5 D7 6 RESET 7 AGND 9 CS 10 11 12 13 14 MODE1 GND VCC GND D− D+ V3.3 ol 8 WR/SK bs USBN9603/4SLB CS 1 28 CLKOUT RD WR/SK 2 27 XOUT 3 26 INTR 4 25 XIN MODE0 5 24 MODE1 23 GND 22 DRQ DACK 6 A0/ALE/SI D0/SO 7 8 21 Vcc GND D1 9 20 D– D2 D3 10 19 11 18 D+ V3.3 D4 D5 12 17 13 16 AGND RESET D6 14 15 D7 28-Pin SO USBN9603/4-28M www.national.
DETAILED SIGNAL/PIN DESCRIPTIONS 1.2.1 Power Supply Name NA Vcc Digital Power Supply (VCC). Power-on reset is detected when the input voltage is at the same level as GND and then raised to the required Vcc level. The power-on reset causes all registers to be set to their reset values, the clock generator to be reset and stalls the CLKOUT output for 214 XIN clock cycles. During this time, no internal register is accessible.
Component (Continued) Parameters Values Tolerance 0 ΝΑ Capacitor C1 15 pF ±20% Capacitor C2 15 pF ±20% Resistor R2 External Elements Choose C1 and C2 capacitors (see Figure 1) to match the crystal’s load capacitance. The load capacitance CL “seen” by the crystal is comprised of C1 in series with C2, and in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 8 pF.
I/O I/O WR Write. Active low write strobe, parallel interface SK MICROWIRE Shift Clock. Mode 2 A0 A0 Address Bus Line. Mode 0, parallel interface ALE Address Latch Enable. Mode 1, parallel interface SI MICROWIRE Serial Input. Mode 2 D0 Data Bus Line D0. Mode 0 AD0 Address/Data Bus LIne AD0. Mode 1 SO MICROWIRE Serial Output. Mode 2 D1 Data Bus Line D1. Mode 0 AD1 I/O D2 Data Bus Line D2. Mode 0 AD2 I/O D3 D4 D5 D6 Address/Data Bus Line AD5. Mode 1 Data Bus Line D6.
Functional Overview The device is a Universal Serial Bus (USB) Node controller compatible with USB Specification, 1.0 and 1.1. It integrates onto a single IC the required USB transceiver with a 3.3V regulator, the Serial Interface Engine (SIE), USB endpoint FIFOs, a versatile (8-bit parallel or serial) interface and a clock generator.
(Continued) CS RD WR/SK DACK DRQ INTR MODE1-0 RESET D7-0/AD7-0/SO Microcontroller Interface (Parallel and Serial) VCC A0/ALE/SI GND Endpoint/Control FIFOs 24 MHz Oscillator Control XIN XOUT Status EP5 et e EP6 RX TX Clock Generator ol EP1 Endpoint0 EP2 PLL x2 SIE Clock Recovery Physical Layer Interface (PHY) USB Event Detect O bs Media Access Controller (MAC) V3.3 Transceiver D+ CLKOUT D- VReg AGND Upstream Port Figure 2. USBN9603/4 Block Diagram 11 www.national.
2.4 (Continued) ENDPOINT PIPE CONTROLLER (EPC) The EPC provides the interface for USB function endpoints. An endpoint is the ultimate source or sink of data. An endpoint pipe facilitates the movement of data between USB and memory, and completes the path between the USB host and the function endpoint. According to the USB specification, up to 31 such endpoints are supported at any given time. USB allows a total of 16 unidirectional endpoints for receive and 16 for transmit.
Parallel Interface The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its addressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1. 3.1 NON-MULTIPLEXED MODE Non-multiplexed mode uses the control pins CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown in Figure 4. This mode is selected by tying both the MODE1 and MODE0 pins to GND.
3.1.1 (Continued) Standard Access Mode The standard access sequence for non-multiplexed mode is to write the address to the ADDR register and then read or write the data from/to the DATA_OUT/DATA_IN register. The DATA_OUT register is updated after writing to the ADDR register. The ADDR register or the DATA_OUT/DATA_IN register is selected with the A0 input. 3.1.2 Burst Mode In burst mode, the ADDR register is written once with the desired memory address of any of the on-chip registers.
3.2 (Continued) MULTIPLEXED MODE Multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE and the bidirectional address data bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to VCC. The address is latched into the ADDR register when ALE is high. Data is output/input with the next active RD or WR signal. All registers are directly accessible in this interface mode. Figure 7 shows basic timing of the interface in Multiplexed mode.
Direct Memory Access (DMA) Support The device supports DMA transfers with an external DMA controller from/to endpoints 1 to 6. This mode uses the device pins DRQ and DACK in addition to the parallel interface pins RD or WR and D7-0 data pins. DMA mode can only be used with parallel interface mode (MODE1 must be grounded). The read or write address is generated internally and the state of the A0/ALE pin is ignored during a DMA cycle. The DMA support logic has a lower priority than the parallel interface.
4.2 (Continued) AUTOMATIC DMA MODE (ADMA) The ADMA mode allows the CPU to transfer independently large bulk or isochronous data streams to or from the USB bus. The application’s DMA controller, together with the ADMA logic, have the capability to split a large amount of data and transfer it in (FIFO size) packets via the USB. In addition, automatic error handling is performed in order to minimize firmware intervention. The number of transferred data stream bytes must be of a modulo 64 size.
(Continued) DRQ DACK WR D7-0 Input et e Figure 12. DMA Write to USBN9603/4 DACK bs RD ol DRQ D7-0 Output Figure 13. DMA Read from USBN9603/4 O USBN9603/USBN9604 4.0 Direct Memory Access (DMA) Support www.national.
MICROWIRE/PLUS Interface The MICROWIRE/PLUS interface allows the device to function as a CPU or microcontroller peripheral via a serial interface. This mode is selected by pulling the MODE1 pin high and the MODE0 pin low. The MICROWIRE/PLUS mode uses the chip select (CS), serial clock (SK), serial data in (SI) and serial data out (SO) pins, as shown in Figure 14. 0x00 Data Out SYNC SK DATA_OUT CS SHIFT SO SI Data In et e DATA_IN ADDR Address CMD1-0 0x3F Register File 5.1 ol Figure 14.
5.2 (Continued) READ AND WRITE TIMING Data is read by shifting in the 2-bit command (CMD and the 6-bit address, RADDR or WADDR) while simultaneously shifting out read data from the previous address. Data can be written in standard or burst mode. Standard mode requires two bytes: one byte for the command and address to be shifted in, and one byte for data to be shifted in. In burst mode, the command and address are transferred first, and then consecutive data is written to that address.
USBN9603/USBN9604 5.0 MICROWIRE/PLUS Interface (Continued) CS 8 Cycles 8 Cycles ADDR Write Data Write Data Undefined Data Read Data Read Data 8 Cycles SK SI SO CMD=11 O bs ol et e Figure 17. Burst Write Timing 21 www.national.
6.1 Functional Description FUNCTIONAL STATES 6.1.1 Line Condition Detection At any given time, the device is in one of the following states (see Section 6.1.2 for the functional state transitions): • • • • NodeOperational Normal operation NodeSuspend Device operation suspended due to USB inactivity NodeResume Device wake-up from suspended state NodeReset Device reset The NodeSuspend, NodeResume, or NodeReset line condition causes a transition from one operating state to another.
USBN9603/USBN9604 6.0 Functional Description (Continued) set_oper NodeOperational 10b suspend_det & set_suspend hw/sw reset reset_det & set_reset NodeReset 00b resume_compl & set_oper resume_det & set_oper NodeResume 01b reset_det &set_reset et e NodeSuspend 11b local_event & sd5_detect & clear_suspend Bold Italics = Transition initiated by firmware ol Notes: 1.
6.2 6.2.1 (Continued) ENDPOINT OPERATION Address Detection Packets are broadcast from the host controller to all the nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to permit optimal use of microcontroller bandwidth. One function address with seven different endpoint combinations is decoded in parallel. If a match is found, then that particular packet is received into the FIFO; otherwise it is ignored.
USBN9603/USBN9604 6.0 Functional Description (Continued) Table 4. USBN9603/4 Endpoint FIFO Sizes TX FIFO RX FIFO Endpoint No.
(Continued) A packet written to the FIFO is transmitted if an IN token for the respective endpoint is received. If an error condition is detected, the packet data remains in the FIFO and transmission is retried with the next IN token. The FIFO contents can be flushed to allow response to an OUT token or to write new data into the FIFO for the next IN token.
(Continued) TCOUNT Transmit FIFO Count. This value indicates how many empty bytes can be filled within the transmit FIFO. This value is accessible by firmware via the TxSx register. Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The Receive FIFOs for the Endpoints 2, 4 and 6 support bulk, interrupt and isochronous USB packet transfers larger than the actual FIFO size.
6.2.3 (Continued) Programming Model Figure 23 illustrates the register hierarchy for event reporting. . MAEV RXEV FWEV TXEV ALTEV NAKEV TXS0 TXC0 et e TXD0 EPC0 RXS0 RXC0 FIFO0 8 byte ol RXD0 TXSx bs TXCx O USBN9603/USBN9604 6.0 Functional Description 6.3 EPCx TFIFOx 64 byte TXDx RXSy RXCx EPCy RFIFOy 64 byte RXDy Figure 23. Register Hierarchy POWER SAVING MODES To minimize the power consumption of the USB node, the device can be set to a static Halt mode.
USBN9603/USBN9604 6.0 Functional Description (Continued) Power-On Reset External RESET 214 cycles Power-Up Delay Power-Up Delay Timeout Wake-Up Event Active Halt Halt On Suspend or Force Halt Figure 24. Power Saving Modes et e The device exits Halt mode in response to one of the following wake-up events: ● A high-to-low transition is detected on the CS pin and the wake-up Enable bit, ENUC in the WKUP register, is set to 1.
Register Set The device has a set of memory-mapped registers that can be read from/written to control the USB interface. Some register bits are reserved; reading from these bits returns undefined data. Reserved register bits should always be written with 0.
USBN9603/USBN9604 7.0 Register Set (Continued) Table 5. Interrupt Output Control Bits INTOC Interrupt Output 0 0 0 Disabled 0 1 Active low open drain 1 0 Active high push-pull 1 1 Active low push-pull Clock Configuration Register (CCONF) bit 7 bit 6 bit 5 CODIS Reserved 0 - r/w - CLKDIV bit 4 bit 3 bit 2 bit 1 bit 0 CLKDIV3-0 1 0 1 1 et e 7.1.2 1 r/w External Clock Divisor.
7.1.4 (Continued) Node Functional State Register (NFSR) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Reserved bit 0 NFS1-0 - 0 - 0 r/w NFS Node Functional State. The firmware should initiate all required state transitions according to the respective status bits in the Alternate Event (ALTEV) register. The valid transitions are shown in Figure 18. The node functional state bits set the node state, as shown in Table 6. Table 6. USB Functional States NFS Node State 7.1.
(Continued) TX_EV Transmit Event. This bit is set if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOx or TXUNDRNx) is set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSx) register are cleared. FRAME This bit is set if the frame counter is updated with a new value.
(Continued) EOP End of Packet. A valid EOP sequence was detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read. SD3 Suspend Detect 3 mS. This bit is set after 3 mS of IDLE is detected on the upstream port, indicating that the device should be suspended.
(Continued) 7.1.10 Transmit Mask Register (TXMSK) When set and the corresponding bit in the TXEV register is set, TX_EV in the MAEV register is set. When cleared, the corresponding bit in the TXEV register does not cause TX_EV to be set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Same Bit Definition as TXEV Register 0 0 0 0 0 0 0 0 bit 3 bit 2 bit 1 bit 0 r/w 7.1.
(Continued) 7.1.13 NAK Event Register (NAKEV) bit 7 bit 6 bit 5 RXFIFO3 RXFIFO2 RXFIFO1 bit 4 bit 3 bit 2 bit 1 bit 0 FIFO0 TXFIFO3 TXFIFO2 TXFIFO1 FIFO0 OUT3-0 0 0 IN3-0 0 0 0 0 CoR 0 0 CoR IN Set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token. This bit is cleared when the register is read. OUT 7.1.
7.2.2 (Continued) FIFO Warning Mask Register (FWMSK) When set and the corresponding bit in the FWEV register is set, WARN in the MAEV register is set. When cleared, the corresponding bit in the FWEV register does not cause WARN to be set.
7.2.5 (Continued) Function Address Register (FAR) This register sets the device function address. The different endpoint numbers are set for each endpoint individually via the Endpoint Control registers. bit 7 bit 6 bit 5 bit 4 bit 3 AD_EN bit 2 bit 1 bit 0 0 0 0 AD6-0 0 0 0 0 0 r/w r/w AD Address. This field holds the 7-bit function address used to transmit and receive all tokens addressed to the device.
(Continued) A DMA request from a transmit endpoint is activated until the request condition clears. If DMOD is set to 0, DMA requests are issued either until the firmware reads the respective Transmit Status (TXSx) register, thus resetting the TX_DONE bit, or if the TX_LAST bit in the Transmit Command (TXCx) register is set by firmware.
(Continued) • If the ADMA bit is cleared (but DEN remains set). In this case, the current operation (if any) is completed. This means that any data in the FIFO is either transmitted or transferred to memory by DMA (if receiving). The DSHLT bit is set only after this has occurred. Note that since DEN remains set, it may need to be cleared later. This commonly is done inside the DSHLT interrupt handler. • If the DEN bit is cleared (ADMA may either remain set, or may be cleared at the same time).
7.2.9 (Continued) Mirror Register (MIR) This is a read only register. Since reading it does not alter the state of the TXSx or RXSx register to which it points, the firmware can freely check the status of the channel. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STAT r STAT Status. This field mirrors the status bits of the transmitter or receiver selected by the DSRC2-0 field in the DMACNTRL register (DMA need not be active or enabled). It corresponds to TXSx or RXSx, respectively. 7.2.
(Continued) AEH Automatic Error Handling. This bit has two different meanings, depending on the current transaction mode: ● Non-Isochronous mode This mode is used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling of packets containing CRC or bit-stuffing errors. If this bit is set during transmit operations, the device automatically reloads the FIFO and reschedules the packet to which the host did not return an ACK.
USBN9603/USBN9604 7.0 Register Set (Continued) 7.2.13 Endpoint Control 0 Register (EPC0) This register controls mandatory Endpoint Control 0. bit 7 bit 6 bit 5 bit 4 STALL DEF Reserved 0 0 - r/w r/w - bit 3 bit 2 bit 1 bit 0 0 0 EP3-0 0 0 r; hardwired to 0 EP Endpoint. This field holds the 4-bit endpoint address. For Endpoint 0, these bits are hardwired to 0000b. DEF Default Address.
(Continued) 7.2.15 Transmit Command 0 Register (TXC0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved IGN_IN FLUSH TOGGLE Reserved TX_EN - 0 0 0 - 0 - r/w r/w HW r/w - r/w HW TX_EN Transmission Enable. This bit enables data transmission from the FIFO. It is cleared by the chip after transmitting a single packet, or a STALL handshake, in response to an IN token. It must be set by firmware to start packet transmission.
(Continued) RX_LAST Receive Last Bytes. Indicates that an ACK was sent upon completion of a successful receive operation. This bit is unchanged for zero length packets. It is cleared when this register is read. TOGGLE This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. This bit is unchanged for zero length packets. It is cleared when this register is read.
(Continued) 7.2.20 Endpoint Control X Register (EPC1 to EPC6) Each unidirectional endpoint has an EPCx register with the bits defined below. bit 7 bit 6 bit 5 bit 4 STALL Reserved ISO EP_EN 0 - 0 0 r/w - r/w r/w bit 3 bit 2 bit 1 bit 0 0 0 EP3-0 0 0 r/w EP Endpoint. This field holds the 4-bit endpoint address. EP_EN Endpoint Enable. When this bit is set, the EP3-0 field is used in address comparison, together with the AD6-0 field in the FAR register. See Section 6.
(Continued) For ISO operation, this bit is set if a frame number LSB match (see “IGN_ISOMSK” bit in Section 7.2.22) occurs, and data was sent in response to an IN token. Otherwise, this bit is reset, the FIFO is flushed and TX_DONE is set. This bit is also cleared when this register is read. TX_URUN Transmit FIFO Underrun. This bit is set if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO.
(Continued) Table 8. Set Transmit FIFO Warning Limit TFWL Bytes Remaining in FIFO 1 0 0 0 TFWL disabled 0 1 ≤4 1 0 ≤8 1 1 ≤ 16 IGN_ISOMSK Ignore ISO Mask. This bit has an effect only if the endpoint is set to be isochronous. If set, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If reset, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared on reset. et e 7.2.
(Continued) For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSx register. SETUP This bit indicates that the setup packet has been received. It is cleared when this register is read. RX_ERR Receive Error. When set, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set, the firmware must flush the respective FIFO. 7.2.
(Continued) 7.2.26 Receive Data X Register (RXD1, RXD2, RXD3) Each of the three Receive Endpoint FIFOs has one Receive Data register with the bits defined below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RXFD r RXFD Receive FIFO Data Byte. See “Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)” in Section 6.2.2 for a description of Endpoint FIFO data handling. The firmware should expect to read only the packet payload data.
USBN9603/USBN9604 7.
Device Characteristics 8.1 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limits beyond which damage to the device may occur. Supply Voltage -0.5V to +7.0V DC Input Voltage -0.5V to VCC +0.5V DC Output Voltage -0.5V to VCC +0.5V Storage Temperature -65˚C to +150˚C Lead Temperature (Soldering 10 seconds) 260˚C ESD Rating1 4.5 KV 1. Human body model; 100 pF discharged through a 1.5 KΩ resistor 8.2 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Operating Ratings et e (3.
Symbol (Continued) Parameter Conditions Min Typ Max Units 0.8 V VIL Input Low Voltage IIL Input Low Current VIN = GND -10 µA IIH Input High Current VIN = VCC 10 µA IOZ Tri-state Leakage VOUT = VCC or GND 10 µA -10 Oscillator Input/Output Signals (XTALIN, XTALOUT) 1.8 V VIH Input High Switching Level4, 5 VIL Input Low Switching Level4, 5 1.0 V CXIN Input Capacitance6 4.0 pF CXOUT Output Capacitance 4.0 pF 3.6 V VO et e Voltage Regulator (3.3V) 3.
(Continued) Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN. 8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00B) (3.0V< VCC < 5.
USBN9603/USBN9604 8.0 Device Characteristics (Continued) CS A0 tAH tAS tWW WR tWC tDS D7-0 Input tDH Valid et e Valid Figure 26. Non-Multiplexed Mode Write Timing (Consecutive Write Cycles Shown) Note: The setup and hold times tAS and tAH are defined relative to the first transition of either CS or WR. Both signals may switch at the same time. PARALLEL INTERFACE TIMING (MODE1-0 = 01B) tAH tCLAL tAVAL tAHAL Parameter Conditions bs Symbol ol (3.0V< VCC < 5.
(Continued) tAH ALE tCLAL t RL CS tALRH RD t RHDZ t AVAL AD7-0 t AHAL t RLDV DATA et e ADDR Figure 27. Multiplexed Mode Interface Read Timing ol tAH ALE tWHAH bs tCLAL CS tWHCH WR O USBN9603/USBN9604 8.0 Device Characteristics AD7-0 tWL t AVAL t DSWH t DHWH t AHAL ADDR DATA Figure 28. Multiplexed Mode Interface Write Timing www.national.
8.6 USBN9603/USBN9604 8.0 Device Characteristics (Continued) DMA SUPPORT TIMING (3.0V< VCC < 5.
8.7 (Continued) MICROWIRE INTERFACE TIMING (MODE1-0 = 10B) Symbol Parameter Condition Min Typ Max Units tSKC SK Cycle Time1 CL = 50 pF 8/MCLK nS tCC Time between two consecutive 8 clock cycles 1 CL = 50 pF 4/MCLK nS tSIH Serial Input Hold Time CL = 50 pF 3/MCLK nS tSOV Serial Output Valid Time CL = 50 pF 3/MCLK nS 1.
USBN9603/USBN9604 Physical Dimensions et e Inches (millimeters) unless otherwise noted O bs ol Laminate Substrate Based Package Order Number USBN9603/4SLB See NS Package Number SLB28AA Molded SO Wide Body Package (WM) Order Number USBN9603/4-28M See NS Package Number M28B 59 www.national.
et e ol bs LIFE SUPPORT POLICY O USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support PC87360 ADVANCE INFORMATION NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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