Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Video editing CCD signal processor LQFP 48 (7x7)

CCD SIGNAL PROCESSOR FOR

SCANNER APPLICATIONS

VSP3200

VSP3210

DESCRIPTION

The VSP3200 and VSP3210 are complete CCD image

processors that operate from single +5V supplies.

This complete image processor includes three Corre-

lated Double Samplers (CDSs) and Programmable

Gain Amplifiers (PGAs) to process CCD signals.

The VSP3200 is interface compatible with the

VSP3210, which is a 16-bit, one-chip product.

The VSP3210 is pin-to-pin compatible with VSP3100,

when in demultiplexed output mode.

The VSP3200 and VSP3210 can be operated from 0°C

to +85°C, and are available in LQFP-48 packages.

FEATURES

F INTEGRATED TRIPLE-CORRELATED

DOUBLE SAMPLER

F OPERATION MODE SELECTABLE:

1-Channel, 3-Channel CCD Mode, 8Msps

F PROGRAMMABLE GAIN AMPLIFIER:

0dB to +13dB

F SELECTABLE OUTPUT MODES:

Normal/Demultiplexed

F OFFSET CONTROL RANGE: ±500mV

F +3V, +5V Digital Output

F LOW POWER: 300mW (typ)

F LQFP-48 SURFACE-MOUNT PACKAGE

RINP

AGND

Clamp

GINP

Clamp

CDS

PGA

BINP

Clamp

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

MUX

Timing Generator

Reference

Circuit

Digital

Output

Control

Offset

Gain

Control

Configuration

Port

16-Bit

A/D

Converter

P/S

WRT

SCLK

REFP

REFN

DRV

B0-B15

(A0-A2, D0-D9)

VSP3200

CK1CLP CK2

ADCCK

REF

TP0

www.ti.com

VSP3200

Not Recommended for New Designs

Summary of content (20 pages)

PAGE 1
Not Recommended for New Designs VSP VSP3200 VSP3210 320 0 www.ti.
PAGE 2
Not Recommended for New Designs SPECIFICATIONS At TA = 25°C, VCC = +5.0V, VDRV = +3.0V, Conversion Rate (fADCCK) = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA Gain = 1, normal output mode, no output load, unless otherwise specified.
PAGE 3
Not Recommended for New Designs ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage: VCC, VDRV ............................................................... +6.5V Supply Voltage Differences: Among VCC ......................................... ±0.1V GND Voltage Differences: Among GNDA ........................................ ±0.1V Digital Input Voltage ............................................... –0.3V to (VCC + 0.3V) Analog Input Voltage ....................................
PAGE 4
Not Recommended for New Designs PIN CONFIGURATION B10 (A0) B9 (D9) B8 (D8) B7 (D7) B6 (D6) B5 (D5) B4 (D4) B3 (D3) B2 (D2) B1 (D1) B0 (D0) LSB LQFP B11 (A1) Top View 36 35 34 33 32 31 30 29 28 27 26 25 B12 (A2) 37 24 OE B13 38 23 VCC B14 39 22 SCLK B15 (MSB) 40 21 SD VDRV 41 20 P/S VCC 42 19 WRT VSP3200Y VCC 43 18 RD AGND 44 17 AGND TP0 45 16 CK2 VREF 46 15 CK1 VCC 47 14 ADCCK AGND AGND RINP AGND 7 8 9 10 11 12 CLP 6 VCC 5 AGND 4 BINP 3 AGN
PAGE 5
Not Recommended for New Designs PIN CONFIGURATION B4, B12 B3, B11 B2, B10 B1, B9 B0, B8 (LSB) NC NC NC NC NC NC LQFP B5, B13 Top View 36 35 34 33 32 31 30 29 28 27 26 25 B6, B14 37 24 OE B7, B15 (MSB) 38 23 VCC NC 39 22 SCLK NC 40 21 SD VDRV 41 20 AGND VCC 42 19 WRT VSP3210Y VCC 43 18 AGND AGND 44 17 AGND TP0 45 16 CK2 VREF 46 15 CK1 VCC 47 14 ADCCK RINP 8 9 10 11 12 CLP AGND 7 VCC AGND 6 AGND 5 BINP 4 AGND 3 GINP 2 AGND 1 REFP 13 VCC
PAGE 6
Not Recommended for New Designs TIMING SPECIFICATIONS VSP3200 AND VSP3210 1-CHANNEL CCD MODE TIMING Pixel 1 Pixel 2 CCD Output tS tS tCK1W-1 tCK1P-1 CK1 tCK2W-1 tCK1CK2-1 tCK2CK1-1 CK2 tCK1ADC tSET tCNV tADCCK2-1 ADCCK Pixel 1 tADCW tADCW tADCP SYMBOL PARAMETER MIN tCK1W-1 tCK1P-1 tCK2W-1 CK1 Pulse Width 1-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising CK1 Rising to ADCCK Falling ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Period
PAGE 7
Not Recommended for New Designs VSP3200 AND VSP 3210 3-CHANNEL CCD MODE TIMING Pixel 1 (R/G/B) Pixel 2 (R/G/B) CCD Output tS tS tCK1W-3 tCK1P-3 CK1 tCK2W-3 tCK1CK2-3 tSET tCK2CK1-3 CK2 tSET tADCCK2-3 tCNV ADCCK (G) (R) tADCW (B) Pixel 1 (R) Pixel 1 (G) Pixel 1 (B) tADCW tADCP SYMBOL PARAMETER MIN tCK1W-3 tCK1P-3 tCK2W-3 CK1 Pulse Width 3-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Pe
PAGE 8
Not Recommended for New Designs DIGITAL DATA OUTPUT SEQUENCE: 1-Ch CCD Mode, (B-Ch: D4 = 1 and D5 = 0) Pixel (n) Pixel (n+1) Pixel (n+8) CCD Output ••• ••• CK1 tSET tSET ••• CK2 tCNV tCNV ••• ADCCK (n) CDS Output B (n) A/D Input (n+1) ••• (n+7) B (n+1) ••• B (n+7) (n+8) B (n+8) B (n) Digital Output (Normal Mode) DIGITAL DATA OUTPUT SEQUENCE: 3-Ch CCD Mode, R > G > B Sequence Pixel (n+1) Pixel (n) Pixel (n+2) CCD Output CK1 tSET CK2 tSET tCNV tCNV ADCCK CDS Output A/D Inpu
PAGE 9
Not Recommended for New Designs VSP3200 TIMING FOR DIGITAL DATA OUTPUT (NORMAL OUTPUT MODE) VSP3200 AND VSP3210 TIMING FOR DIGITAL DATA OUTPUT (DEMULTIPLEXED OUTPUT MODE) P/S P/S(1) tOES tOES tOEP tOEW OE OE tOER ADCCK t3E (n) (n) tDODH tOER (n+1) ADCCK tDODH tDOD n (B6-B13) n (B0-B5) PARAMETER MIN A/D Output Enable Setup Time Output Enable Time 3-State Enable Time OE Pulse Width Digital Data Output Delay, High-Byte Digital Data Output Delay, Low-Byte Parallel Port Setup Time 20 (n+2
PAGE 10
Not Recommended for New Designs THEORY OF OPERATION INTRODUCTION The VSP3200 and VSP3210 are complete mixed-signal ICs that contain all of the key features associated with the processing of the CCD line sensor output signal in scanners, photo copiers, and similar applications. See the simplified block diagram on page 1 for details.
PAGE 11
Not Recommended for New Designs The VSP3210 can be operated in Demultiplexed mode as the digital output (B13-based Big Endian Format), as shown in Table I. The VSP3210 outputs the high byte (upper 8 bits) by pin 31 through pin 38 at the rising edge of ADCCK HIGH, then outputs the low byte (lower 8 bits) by pin 31 through pin 38 at the falling edge of ADCCK (as shown in Table II). An 8-bit interface can be used between the VSP3200 and the Digital Signal Processor, allowing for a low-cost system solution.
PAGE 12
Not Recommended for New Designs INPUT CLAMP The input clamp should be used for 1-Channel and 3-Channel CCD mode, and enabled when both CLP and CK1 are set to HIGH. Bit Clamp: the input clamp is always enabled. Line Clamp: enables during the dummy pixel interval at every horizontal line, and disables during the effective pixel interval. Generally, “Bit Clamp” is used for many scanner applications, however “Line Clamp” is used instead of “Bit Clamp” when the clamp noise is impressive.
PAGE 13
Not Recommended for New Designs other system circuits, as it would affect the reference voltage of the A/D converter and prevent proper A/D conversion. • External Reference: to set the external reference mode, D2 of the configuration register must be set to “1”. In external reference mode, VREF operates as an analog voltage input pin. Inputting half the voltage necessary for the full-scale voltage range (e.g.: 1.7V applied for a necessary 3.4Vp-p input range), with a reference voltage range from 0.25V to 1.
PAGE 14
Not Recommended for New Designs OFFSET REGISTER Offset Registers control the analog offset input to channels prior to the PGA. There is a 10-bit Offset Register on each channel. The offset range varies from –500mV to +500mV. The Offset Register uses a straight binary code. All “0s” corresponds to –500mV, and all “1s” corresponds to +500mV of the offset adjustment. The register code (200H) corresponds to 0mV of the offset adjustment.
PAGE 15
Not Recommended for New Designs ® PACKAGE DRAWING MPQF102
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device VSP3210Y/2K Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 9.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.5 2.0 12.0 16.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP3210Y/2K LQFP PT 48 2000 367.0 367.0 38.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.