XIO1100 Data Manual Literature Number: SLLS690C April 2006 Revised August 2011
Contents Contents Section 1 2 3 4 5 6 XIO1100 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Figure 2−1. Figure 4−1. Figure 4−2. Figure 4−3. Figure 4−4. Figure 5−1. Figure 5−2. ii Page XIO1100 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TI−PIPE Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TI−PIPE Data Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table Table 2−1. Table 2−2. Table 2−3. Table 2−4. Table 2−5. Page Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX_STATUS Loopback Detection Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-pin GGB Signal Name Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features 1 XIO1100 Features D X1 PCI Expresst Serial Link − PCI Express 1.1 Compliant − Selectable Reference Clock (100 MHz, 125 MHz) − Low-Power Capability TI and MicroStar BGA are trademarks of Texas Instruments Incorporated PCI Express is a trademark of PCI−SIG 2 D TI-PIPE MAC Interface D D − Source-Synchronous TX and RX Ports − 125 MHz TX/RX Clocks − Selectable 16-Bit SDR or 8-Bit DDR Mode 100-Pin MicroStart BGA Package Selectable 1.5−V or 1.8−V LVCMOS Buffers.
Description 2.2 Functional Description The XIO1100 meets all of the requirements for a PCI−Express PHY as defined by Section 4, Physical Layer Specifications, of the PCI−SIG document PCI Express Base Specification. The XIO1100 conforms to the functional behavior described in PHY Interface for the PCI Expresst Architecture by Intel Corporation. There are only two differences between the XIO1100 TI−PIPE interface and the Intel PIPE interface.
Description 2.3.1 P0 P0 is the normal operation state for the XIO1100. The POWERDOWN[1:0] input signals define which of the three power states that an XIO110 is in at any given time. In states P0, P0s, and P1, the XIO1100 is required to keep P_CLK operational. For all state transitions between these three states, the XIO1100 indicates successful transition into the designated power state by a single cycle assertion of PHY_STATUS.
Description 2.6 Receiver Detection While in the P1 power state, XIO1100 can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. The MAC requests XIO1100 to do a receiver detect sequence by asserting TXDETECTRX/LOOPBACK high. Upon completion of the receiver detection operation, the XIO1100 asserts PHY_STATUS high for one RX_CLK cycle.
Description 2.8.1 8B/10B Decode Error When XIO1100 detects an 8B/10B decode error, it asserts an EDB (0xFE) symbol in the data on the RX_DATA[15:0] where the bad byte occurred (only the erroneous byte is replaced with the EDB symbol; the other byte is still valid data). In the same RX_CLK clock cycle that the EDB symbol is asserted on the RX_DATA[15:0] bus, the 8B/10B decode error code (100b) is asserted on the RX_STATUS[2:0] bus.
Description 2.13 Terminal Assignments The XIO1100 is packaged in a 100-pin GGB BGA package. See Section 6 for GGB-package terminal diagram. Table 2−3 lists the terminal assignments in terminal-number order with corresponding signal names for the GGB package. Table 2−4 lists the terminal assignments arranged in alphanumerical order by signal name with corresponding terminal numbers for the GGB package. Table 2−3.
Description Table 2−4.
Description 2.14 Terminal Descriptions Table 2−5 describes the XIO1100 terminals. The terminals are grouped by functionality. Table 2−5. XIO1100 Terminals TERMINAL NAME I/O DESCRIPTION NO. PIPE INTERFACE /RESET N11 I Reset the device. This signal is active low and asynchronous.
Description Table 2−5. XIO1100 Terminals (Continued) TERMINAL TX_ELECIDLE N9 I/O I DESCRIPTION Forces TXN/TXP outputs to electrical idle. When de−asserting low while in P0 state (POWERDOWN[1:0] = 00), indicates that valid data is on the TXDATA bus and that this data should be transmitted. When asserted high while in P0s state (POWERDOWN[1:0] = 01), always asserted for P0s state. When asserted high while in P1 state (POWERDOWN[1:0] = 10), always asserted for P1 state.
Description Table 2−5.
Description Table 2−5. XIO1100 Terminals (Continued) TERMINAL CLK_SEL L6 I/O I DESCRIPTION Clock Select This input, when asserted low during /RESET transitioning from low to high, selects the 100 MHz differential clock source. A 100MHz clock source has to be applied to REFCLK+ and REFCLK−. This input, when asserted high during /RESET transitioning to high, selects the 125 MHz single ended clock source. A 125 MHz clock source has to be applied to REFCLK+. REFCLK− has to be connected to VSS.
Electrical Characteristics 3 Electrical Characteristics 3.1 Absolute Maximum Ratings† Supply voltage range: Input voltage range, 3.3 V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V 1.8 V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 1.95 V 1.5 V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 1.65 V VI: PCI Express (RX) .
Electrical Characteristics 3.3 PCI Express Differential Transmitter Output Ranges PARAMETER UI Unit interval TERMINALS TXP, TXN MIN NOM MAX 399.88 400 400.12 UNIT ps COMMENTS Each UI is 400 ps ±300 ppm. UI does not account for SSC−dictated variations. See Note 4. VTX–DIFFp–p Differential peak–to– peak output voltage TXP, TXN VTX–DE–RATIO De–emphasized differential output voltage (ratio) TXP, TXN 0.8 1.2 V VTX–DIFFp–p = 2*|VTXP − VTXN| See Note 5. −3.0 −3.5 −4.
Electrical Characteristics PARAMETER VTX–IDLE–DIFFp TERMINALS TXP, TXN MIN NOM 0 MAX 20 UNIT mV Electrical idle differential peak output voltage VTX–RCV–DETECT See Note 5. TXP, TXN 600 mV The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. 3.6 V The allowed dc common mode voltage under any condition.
Electrical Characteristics PARAMETER TERMINALS ZTX–DC MIN TXP, TXN 40 TXP, TXN 75 NOM MAX UNIT COMMENTS Ω Required TXP as well as TXN dc impedance during all states nF All transmitters are ac–coupled and are required on the PWB. Transmitter dc impedance CTX 200 AC coupling capacitor NOTES: 4. No test load is necessarily associated with this value. 5. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. 6.
Electrical Characteristics PARAMETER TERMINALS TRX–EYE–MEDIAN–to–MAX–JITTER RXP, RXN MIN NOM MAX 0.3 UNIT COMMENTS UI Jitter is defined as the measurement variation of the crossing points (VRX–DIFFp–p = 0 V) in relation to recovered TX UI. A recovered TX UI is calculated over 3500 consecutive UIs of sample data. Jitter is measured using all edges of the 250 consecutive UIs in the center of the 3500 UIs used for calculating the TX UI.
Electrical Characteristics PARAMETER VRX–IDLE–DET–DIFFp–p TERMINALS RXP, RXN MIN 65 NOM MAX UNIT COMMENTS 175 mV VRX–IDLE–DET–DIFFp–p = 2*|VRXP − VRXN| measured at the receiver package terminals 10 ms An unexpected electrical idle (VRX–DIFFp–p < VRX–IDLE–DET–DIFFp–p) must be recognized no longer than TRX–IDLE–DET–DIFF–ENTER–TIME to signal an unexpected idle condition.
Electrical Characteristics 3.5 Express Differential Reference Clock Input Ranges PARAMETER TERMINALS fIN–DIFF REFCLK+ Differential input frequency REFCLK− fIN–SE REFCLK+ MIN NOM MAX UNIT 100 MHz The input frequency is 100 MHz + 300 ppm and − 2800 ppm including SSC–dictated variations. 125 MHz The input frequency is 125 MHz + 300 ppm and − 300 ppm. Single–ended input frequency VRX–DIFFp–p REFCLK+ Differential input peak–to–peak voltage REFCLK− VIH–SE COMMENTS 0.175 1.
Electrical Characteristics 3.6 Electrical Characteristics Over Recommended Operating Conditions (VDD_IO) PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage (Note 16) VDD_IO 0.7 VDD_IO VDD_IO V VIL Low-level input voltage (Note 16) VDD_IO 0 0.
Timing Diagrams 4 Timing Diagrams TI−PIPE Input Timing tcyc TX_CLK TxData[7:0] (DDR mode) TxDataK[0] (DDR mode) tfsu trsu tfh TxData[15:0] (SDR mode) TxDataK[1:0] (SDR mode) TxDetectRx/Loopback TxElecIdle TxCompliance RxPolarity PowerDown[1:0] tfh trsu tfh Figure 4−1. TI−PIPE Input Timing 20 PARAMETER DESCRIPTION VALUE tcyc Period, TX_CLK 8 ns (TYP) trsu Input Setup to TX_CLK rising 1.3 ns (MAX) trh Input Hold from TX_CLK rising 0.1 ns (MIN) tfsu Input Setup to TX_CLK falling 1.
Timing Diagrams TI−PIPE Data Output Timing tcyc RX_CLK RxData[7:0] (DDR mode) RxDataK[0] (DDR mode) trco tfh tfh tfco RxData[15:0] (SDR mode) RxDataK[1:0] (SDR mode) RxValid PhyStatus RxElecIdle RxStatus[2:0] trco tfh Figure 4−2. TI−PIPE Data Output Timing PARAMETER DESCRIPTION VALUE tcyc Period, RX_CLK 8.0 ns (TYP) trco Clock to output, RX_CLK rising 2.0 ns (MAX) trh Output hold, RX_CLK rising 0.7 ns (MIN) tfco Clock to output, RX_CLK falling 2.
Timing Diagrams TI−PIPE Output Functional Timing RX_CLK RxData[7:0] (DDR mode) RxDataK[0] (DDR mode) RxData[15:0] (SDR mode) RxDataK[1:0] (SDR mode) SYMBOL (N) SYMBOL (N+1) RxData[7:0] − SYMBOL (N) RxData[15:8] − SYMBOL (N+1) RxValid PhyStatus RxElecIdle RxStatus[2:0] Figure 4−3.
Timing Diagrams TI−PIPE Input Functional Timing TX_CLK TxData[7:0] (DDR mode) TxDataK[0] (DDR mode) TxData[15:0] (SDR mode) TxDataK[1:0] (SDR mode) SYMBOL (N) SYMBOL (N+1) TxData[7:0] − SYMBOL (N) TxData[15:8] − SYMBOL (N+1) TxDetectRx/Loopback TxElecIdle TxCompliance RxPolarity PowerDown[1:0] Figure 4−4.
Application Information 5 Application Information 5.1 Component Connection Details regarding connection of components to the various terminals of the XIO1100 are discussed primarily in entries for each terminal in the terminal functions table.
Application Information 5.2 XIO1100 Component Placement The filter network on VDD_33_COMB, VDD_33_COMB_IO, and VDD_15_COMB needs to be placed as close as possible to each pin (specifically H11, L13, and L12). It is recommended that the trace width for these three pins be at least 10 mils. The R0 and R1 terminals connect to an external resistor to set the drive current for the PCI Express TX driver. The recommended resistor value is 14,560-Ω with 1% tolerance. A 14,560-Ω resistor is a custom value.
Application Information 5. When designing filters associated with power distribution, the power supply is a low-impedance source, and the device power terminals are a low-impedance load. The best filter for this application is a T filter. See Figure 5−2 for a T filter circuit. Some systems may require this type of filter design if the power supplies or nearby components are exceptionally noisy.
Application Information 5.4 PCIe Layout Guidelines The XIO1100 TXP and TXN terminals comprise a low-voltage, 100-Ω differentially driven signal pair. The RXP and RXN terminals for the XIO1100 receive a low-voltage, 100-Ω differentially driven signal pair. The XIO1100 has integrated 50-Ω termination resistors to VSS on both the RXP and RXN terminals, eliminating the need for external components. Each lane of the differential signal pair must be ac-coupled.
Application Information The XIO1100 is optimized for this type of system clock design. The REFCLK+ and REFCLK− terminals provide differential reference clock inputs to the XIO1100. The circuit board routing rules associated with the 100-MHz differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules already described. The only difference is that the differential reference clock does not require series capacitors.
Mechanical Data 6 Mechanical Data June 2006 Revised August 2011 SLLS690C 29
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