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XIO2001

XIO2001 PCI Express™ to PCI Bus Translation Bridge

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SCPS212G

May 2009–Revised December 2012

Summary of content (133 pages)

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XIO2001 XIO2001 PCI Express™ to PCI Bus Translation Bridge Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Contents 1 ........................................................................................................................ 9 ...................................................................................................................... 9 Overview .......................................................................................................................... 10 2.1 Description ........................................
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XIO2001 www.ti.com 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 4.56 4.57 4.58 4.59 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Primary Latency Timer Register ......................................................................................... Header Type Register ..........................................
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.60 4.61 4.62 4.63 4.64 4.65 4.66 4.67 4.68 4.69 4.70 4.71 4.72 4.73 4.74 4.75 4.76 4.77 4.78 5 6 7 4 GPIO Data Register ....................................................................................................... TL Control and Diagnostic Register 0 .................................................................................. Control and Diagnostic Register 1 ..........................................................................
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XIO2001 www.ti.com 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Nominal Power Consumption .......................................................................................... PCI Express Differential Transmitter Output Ranges ............................................................... PCI Express Differential Receiver Input Ranges ....................................................................
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com List of Figures 2-1 XIO2001 ZGU MicroStar BGA Package (Bottom View) ..................................................................... 13 2-2 XIO2001 ZAJ MicroStar BGA Package (Bottom View)...................................................................... 14 2-3 XIO2001 PNP PowerPad™ HTQFP Package (Top View) .................................................................. 14 3-1 XIO2001 Block Diagram ...........................
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 List of Tables ........................................................................................................ 2-1 Power Supply Terminals 2-2 Ground Terminals ................................................................................................................ 16 2-3 Combined Power Output Terminals 2-4 PCI Express Terminals .............................................................................................
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 8 www.ti.com .............................................................................................. ............................................................................ Serial-Bus Control and Status Register Description ...
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 XIO2001 PCI Express™ to PCI Bus Translation Bridge Check for Samples: XIO2001 1 Introduction 1.1 Features 1 234 • Full ×1 PCI Express Throughput • Fully Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 • Fully Compliant with PCI Express Base Specification, Revision 2.0 • Fully Compliant with PCI Local Bus Specification, Revision 2.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 2 www.ti.com Overview The Texas Instruments XIO2001 is a PCI Express to PCI local bus translation bridge that provides full PCI Express and PCI local bus functionality and performance. 2.1 Description The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0.
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XIO2001 www.ti.com 2.3 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Documents Conventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 1 2 3 4 N C/BE[3] AD25 AD27 AD30 M AD20 AD22 AD24 AD26 L AD18 AD19 AD21 K AD16 AD17 J IRDY H TRDY www.ti.
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XIO2001 www.ti.
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XIO2001 www.ti.
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XIO2001 www.ti.com 2.6 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Terminal Descriptions The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 2-2.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 2-4.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 2-5.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 2-5.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 2-6. JTAG Terminals (continued) SIGNAL ZGU BALL # ZAJ BALL # PNP PIN # I/O TYPE CELL TYPE CLAMP RAIL L09 L09 60 I LV CMOS VDD_33 JTAG_TRST EXTERNAL PARTS DESCRIPTION JTAG test reset. This terminal provides Optional for asynchronous initialization of the TAP controller. Note: This terminal has an internal Optional pullup active pullup resistor. The pullup is resistor active at all times.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 2-7. Miscellaneous Terminals (continued) SIGNAL GPIO3 // SDA ZGU BALL # ZAJ BALL # PNP PIN # I/O TYPE CELL TYPE CLAMP RAIL N11 L08 58 I/O LV CMOS VDD_33 EXTERNAL PARTS Optional pullup resistor DESCRIPTION GPIO3 or serial-bus data. This terminal functions as serial-bus data if a pullup resistor is detected on SCL or when the SBDETECT bit is set in the Serial Bus Control and Status Register (see Section 4.58).
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3 www.ti.com Feature/Protocol Descriptions This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI Express interface and the PCI bus interface is located at the bottom of the diagram.
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XIO2001 www.ti.com 3.1.1 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Power-Up Sequence 1. 2. 3. 4. 5. Assert PERST to the device. Apply 1.5-V and 3.3-V voltages. Apply PCIR clamp voltage. Apply a stable PCI Express reference clock. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: – Wait a minimum of 100 μs after applying a stable PCI Express reference clock.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3.1.2 www.ti.com Power-Down Sequence 1. 2. 3. 4. Assert PERST to the device. Remove the reference clock. Remove PCIR clamp voltage. Remove 3.3-V and 1.5-V voltages. See the power-down sequencing diagram in Figure 3-3. If the VDD_33_AUX terminal is to remain powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in Figure 33. VDD_15 and VDDA_15 VDD_33 and VDDA_33 PCIR REFCLK PERST Figure 3-3.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 3-1. XIO2001 Reset Options (continued) RESET OPTION PCI Express reset input PERST XIO2001 FEATURE This XIO2001 input terminal is used by an upstream PCI Express device to generate a PCI Express reset and to signal a system power good condition. When PERST is asserted low, the XIO2001 generates an internal PCI Express reset as defined in the PCI Express specification.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3.3.2 www.ti.com Beacon The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65, General Control Register, for details.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 3-3. Messages Supported by the Bridge (continued) SUPPORTED BRIDGE ACTION Set_Slot_Power_Limit MESSAGE Yes Received and processed Unlock No Discarded Hot plug messages No Discarded Advanced switching messages No Discarded Vendor defined type 0 No Unsupported request Vendor defined type 1 No Discarded All supported message transactions are processed per the PCI Express Base Specification. 3.4 3.4.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from floating To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at offset DAh (see Section 4.68) is read.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 The bridge has a dedicated SERIRQ terminal for all PCI bus devices that support serialized interrupts. This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never generates an IRQ interrupt or MSI message.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the PCI bus clock input (CLK).
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 3-6.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3.7 www.ti.com PCI Interrupt Conversion to PCI Express Messages The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages. Table 3-7, Figure 3-7, and Figure 3-8 illustrate the format for both the assert and deassert INTx messages. Table 3-7. Interrupt Mapping In The Code Field INTERRUPT CODE FIELD INTA 00 INTB 01 INTC 10 INTD 11 Figure 3-7. PCI Express ASSERT_INTX Message Figure 3-8.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Figure 3-9. PCI Express PME Message 3.9 PCI Express to PCI Bus Lock Conversion The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal is a dedicated output that is enabled by setting bit 12 in the general control register at offset D4h. See Section 4.65, General Control Register, for details.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Once the bridge has ownership of LOCK, the bridge initiates the lock read as a memory read transaction on the PCI bus. When the target of the locked-memory read returns data, the bridge is considered locked and all transactions not associated with the locked sequence are blocked by the bridge. Figure 3-11.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3.10.1 Serial-Bus Interface Implementation To enable the serial-bus interface, a pullup resistor must be implemented on the SCL signal. At the rising edge of PERST or GRST, whichever occurs later in time, the SCL terminal is checked for a pullup resistor. If one is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58) is set.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3-15 illustrates the acknowledge protocol.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Figure 3-17. Serial-Bus Protocol – Byte Read Figure 3-18 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred. The number of transferred data bytes is controlled by the bridge master.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 3-8.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 3.10.4 Accessing Serial-Bus Devices Through Software The bridge provides a programming mechanism to control serial-bus devices through system software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3-9 lists the registers that program a serial-bus device through software. Table 3-9.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data parity error is detected, then this information is passed to the PCI Express interface. To do this, the bridge sets the EP bit in the upstream PCI Express header. 3.13 General-Purpose I/O Interface Up to five general-purpose input/output (GPIO) terminals are provided for system customization. These GPIO terminals are 3.3-V tolerant.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 3-10. Clocking In Low Power States CLOCK SOURCE D0/L0 D1/L1 D2/L1 D3/L2/L3 PCI express reference clock input (REFCLK) On On On On/Off Internal PCI bus clock to bridge function On Off Off Off The link power management (LPM) state machine manages active state power by monitoring the PCI Express transaction activity.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4 www.ti.com Classic PCI Configuration Space The programming model of the XIO2001 PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header. All bits marked with a are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-1.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.3 www.ti.com Command Register The command register controls how the bridge behaves on the PCI Express interface. See Table 4-2 for a complete description of the register contents. PCI register offset: 04h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-2.
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XIO2001 www.ti.com 4.4 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Status Register The status register provides information about the PCI Express interface to the system. See Table 4-3 for a complete description of the register contents. PCI register offset: 06h Register type: Read-only, Read/Clear Default value: 0010h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 Table 4-3.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.5 www.ti.com Class Code and Revision ID Register This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI-to-PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte (03h).
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XIO2001 www.ti.com 4.7 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Primary Latency Timer Register This read-only register has no meaningful context for a PCI Express device and returns 00h when read. PCI register offset: 0Dh Register type: Read only Default value: 00h BIT NUMBER RESET STATE 4.8 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Header Type Register This read-only register indicates that this function has a type one PCI header.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-5. Device Control Base Address Register Description BIT FIELD NAME 31:12 ADDRESS 11:4 ACCESS R or RW DESCRIPTION Memory Address. The memory address field for XIO2001 uses 20 read/write bits indicating that 4096 bytes of memory space are required. While less than this is actually used, typical systems will allocate this space on a 4K boundary.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.14 Secondary Latency Timer Register This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles. PCI register offset: 1Bh Register type: Read/Write Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.15 I/O Base Register This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.17 Secondary Status Register The secondary status register provides information about the PCI bus interface. See Table 4-8 for a complete description of the register contents. PCI register offset: 1Eh Register type: Read-only, Read/Clear Default value: 02X0h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-8.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4-9 for a complete description of the register contents. PCI register offset: 20h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-9.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-11. Prefetchable Memory Base Register Description BIT FIELD NAME 15:4 PREBASE 3:0 64BIT ACCESS DESCRIPTION RW Prefetchable memory base. Defines the lowest address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.23 Prefetchable Limit Upper 32-Bit Register This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 414 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-16. I/O Limit Upper 16-Bit Register Description BIT FIELD NAME 15:0 IOLIMIT ACCESS DESCRIPTION I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that determines when to forward I/O transactions downstream. These bits correspond to address bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh. RW 4.
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XIO2001 www.ti.com 4.29 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Bridge Control Register The bridge control register provides extensions to the command register that are specific to a bridge. See Table 4-17 for a complete description of the register contents. PCI register offset: 3Eh Register type: Read-only, Read/Write, Read/Clear Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-17.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-17. Bridge Control Register Description (continued) BIT 5 FIELD NAME MAM ACCESS RW DESCRIPTION Master abort mode. This bit controls the behavior of the bridge when it receives a master abort or an unsupported request. 0 = Do not report master aborts. Returns FFFF FFFFh on reads and discard data on writes (default) 1 = Respond with an unsupported request on PCI Express when a master abort is received on PCI.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-17. Bridge Control Register Description (continued) BIT 0 FIELD NAME ACCESS DESCRIPTION RW Parity error response enable. Controls the bridge's response to data, uncorrectable address, and attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning, from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless of the setting of this bit.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.33 Subsystem ID Register This register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-18. Power Management Capabilities Register Description BIT FIELD NAME ACCESS 15:11 PME_SUPPORT R PME support. This 5-bit field indicates the power states from which the bridge may assert PME. Because the bridge never generates a PME except on a behalf of a secondary device, this field is read-only and returns 00000b.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.38 Power Management Bridge Support Extension Register This read-only register indicates to host software what the state of the secondary bus will be when the bridge is placed in D3. See Table 4-20 for a complete description of the register contents. PCI register offset: 4Eh Register type: Read-only Default value: 40h BIT NUMBER RESET STATE 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-20.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.41 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 70h pointing to the subsystem ID capabilities registers. PCI register offset: 51h Register type: Read-only Default value: 70h BIT NUMBER RESET STATE 7 0 6 1 5 1 4 1 3 0 2 0 1 0 0 0 4.42 MSI Message Control Register This register controls the sending of MSI messages.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-22. MSI Message Lower Address Register Description BIT FIELD NAME 31:2 ADDRESS 1:0 RSVD ACCESS DESCRIPTION RW System specified message address R Reserved. Returns 00b when read. 4.
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XIO2001 www.ti.com 4.46 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 PCI Express Capability ID Register This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor ID capabilities. The register returns 10h when read. PCI register offset: 70h Register type: Read-only Default value: 10h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 4.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.49 Device Capabilities Register The device capabilities register indicates the device specific capabilities of the bridge. See Table 4-25 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.50 Device Control Register The device control register controls PCI Express device specific parameters. See Table 4-26 for a complete description of the register contents. PCI register offset: 78h Register type: Read-only, Read/Write Default value: 2000h BIT NUMBER RESET STATE 15 0 14 0 13 1 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-26.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-26. Device Control Register Description (continued) BIT 1 FIELD NAME ACCESS NFERE DESCRIPTION RW Nonfatal error reporting enable. If this bit is set, then the bridge is enabled to send ERR_NONFATAL messages to the root complex when a system error event occurs. 0 = Do not report nonfatal errors to the root complex (default) 1 = Report nonfatal errors to the root complex 0 CERE RW Correctable error reporting enable.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-28. Link Capabilities Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:24 PORT_NUM R Port number. This field indicates port number for the PCI Express link. This field is read-only 00h indicating that the link is associated with port 0. 23:22 RSVD R Reserved. Return 00b when read. 21 LBN_CAP R Link bandwidth notification. This bit is hardwired to 0b since this field is not applicable to a bridge.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-29. Link Control Register Description (continued) BIT 8 FIELD NAME ACCESS CPM_EN RW DESCRIPTION Clock Power Management Enable. This bit is used to enable the bridge to use CLKREQ for clock power management 0 = Clock Power Management is disabled. CLKREQ is held low.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-30. Link Status Register Description (continued) BIT 12 FIELD NAME ACCESS DESCRIPTION R Slot clock configuration. This bit indicates that the bridge uses the same physical reference clock that the platform provides on the connector. If the bridge uses an independent clock irrespective of the presence of a reference on the connector, then this bit must be cleared.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.57 Serial-Bus Slave Address Register The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle on the serial interface. See Table 4-31 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-32. Serial-Bus Control and Status Register Description (continued) BIT 2 (1) FIELD NAME ACCESS DESCRIPTION RW Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source for the serial interface clock. SBTEST 0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default) 1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz 1 (1) SB_ERR RCU Serial-bus error.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.60 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL). The default value at power up depends on the state of the GPIO terminals as they default to generalpurpose inputs.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-35. Control and Diagnostic Register 0 Description (continued) BIT FIELD NAME 18 ALT_ERROR_REP ACCES S RW DESCRIPTION Alternate Error Reporting. This bit controls the method that the XIO2001 uses for error reporting. 0 = Advisory Non-Fatal Error reporting supported (default) 1 = Advisory Non-Fatal Error reporting not supported 17:16 RSVD R 15:14 (1) RSVD RW 13:12 RSVD R 11:7 (1) RSVD RW R Reserved.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-36. Control and Diagnostic Register 1 Description (continued) BIT 1:0 (1) FIELD NAME ACCESS RSVD DESCRIPTION RW Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another mechanism, then the value written into this field must be 00b. 4.63 Control and Diagnostic Register 2 The contents of this register are used for monitoring status and controlling behavior of the bridge.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-38. Subsystem Access Register Description ACCESS DESCRIPTION 31:16 (1) BIT SubsystemID RW Subsystem ID.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.65 General Control Register This read/write register controls various functions of the bridge. See Table 4-39 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-39. General Control Register Description (continued) BIT 22:20 (1) FIELD NAME POWER_OVRD ACCESS RW DESCRIPTION Power override. This bit field determines how the bridge responds when the slot power limit is less than the amount of power required by the bridge and the devices behind the bridge. 000 = Ignore slot power limit (default). 001 = Assert the PWR_OVRD terminal.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-39. General Control Register Description (continued) BIT 9:8 (2) FIELD NAME ACCESS MIN_POWER_S CALE RW DESCRIPTION Minimum power scale. This value is programmed to indicate the scale of bits 7:0 (MIN_POWER_VALUE). 00 01 10 11 7:0 (2) MIN_POWER_VA LUE RW = = = = 1.0x 0.1x 0.01x (default) 0.001x Minimum power value. This value is programmed to indicate the minimum power requirements.
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XIO2001 www.ti.com 4.67 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Clock Mask Register This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the clock outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater than the power required. See Table 4-41 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.68 www.ti.com Clock Run Status Register The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 442 for a complete description of the register contents. PCI register offset: DAh Register type: Read-only Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-42. Clock Run Status Register Description BIT 7:1 0 FIELD NAME RSVD ACCESS R DESCRIPTION Reserved.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.69 Arbiter Control Register The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration tier. See Table 4-43 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-43. Clock Control Register Description (continued) BIT FIELD NAME ACCESS 0 (1) DESCRIPTION GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration scheme.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.70 Arbiter Request Mask Register The arbiter request mask register enables and disables support for requests from specific masters on the secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an arbiter time-out. See Table 4-44 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 4.71 Arbiter Time-Out Status Register The arbiter time-out status register contains the status of each request (request 5–0) time-out. The timeout status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See Table 4-45 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-46. Serial IRQ Mode Control Register Description BIT 7:4 FIELD NAME ACCESS RSVD DESCRIPTION R Reserved. Returns 0h when read. Start frame pulse width. Sets the width of the start frame for a SERIRQ stream. 00 = 4 clocks (default) 3:2 (1) START_WIDTH RW 01 = 6 clocks 10 = 8 clocks 11 = Reserved Poll mode. This bit selects between continuous and quiet mode.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-47.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 4.74 Serial IRQ Status Register This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are defined as edge mode in the serial IRQ edge control register are not reported in this status register. See Table 4-48 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 4-48. Serial IRQ Status Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted. 6 (1) IRQ6 RCU 0 = Deasserted 1 = Asserted IRQ 5 asserted. This bit indicates that the IRQ5 has been asserted. 5 (1) IRQ5 RCU 0 = Deasserted 1 = Asserted IRQ 4 asserted. This bit indicates that the IRQ4 has been asserted.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 4-49. Pre-Fetch Agent Request Limits Register Description BIT FIELD NAME 15:12 RSVD ACCESS DESCRIPTION R Reserved. Returns 0h when read. Request count limit. Determines the number of Pre-Fetch reads that takes place in each burst. 11:8 (1) PFA_REQ_ CNT_LIMIT RW 4'h0 = Auto-prefetch agent is disabled. 4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 BIT NUMBER RESET STATE 15 0 14 0 13 0 www.ti.com 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 0 0 Table 4-50. Cache Timer Transfer Limit Register Description BIT (1) FIELD NAME 15:8 RSVD 7:0 (1) CACHE_TMR_XFR _LIMIT ACCESS R DESCRIPTION Reserved. Returns 00h when read. RW Number of PCI cycle starts that have to occur without a read hit on the completion data buffer, before the cache data can be discarded.
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XIO2001 www.ti.com 5 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 PCI Express Extended Configuration Space The programming model of the PCI Express extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI Express extended configuration map uses the PCI Express advanced error reporting capability.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 5.2 www.ti.com Next Capability Offset/Capability Version Register This read-only register identifies the next location in the PCI Express extended capabilities link list. The upper 12 bits in this register shall be 000h, indicating that the Advanced Error Reporting Capability is the last capability in the linked list. The least significant four bits identify the revision of the current capability block as 1h.
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XIO2001 www.ti.com 5.4 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Uncorrectable Error Mask Register The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-3 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 5-3. Uncorrectable Error Mask Register Description (continued) BIT 3:0 5.5 FIELD NAME ACCESS RSVD R DESCRIPTION Reserved. Returns 0h when read. Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 5-4. Uncorrectable Error Severity Register Description (continued) BIT 11:6 FIELD NAME ACCESS RSVD DESCRIPTION R Reserved. Returns 000 000b when read. SD error severity. Not supported, returns 1b when read. 5 SD_ERROR_SEVR R 4 (1) DLL_ERROR_SEVR RW Data link protocol error severity 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL 3:1 RSVD R Reserved.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 5.7 www.ti.com Correctable Error Mask Register The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-6 for a complete description of the register contents.
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XIO2001 www.ti.com 5.8 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Advanced Error Capabilities and Control Register The advanced error capabilities and control register allows the system to monitor and control the advanced error reporting capabilities. See Table 5-7 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 5.10 Secondary Uncorrectable Error Status Register The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5-8 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 5.11 Secondary Uncorrectable Error Mask Register The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-9 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 5.12 Secondary Uncorrectable Error Severity The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5-10 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 5.13 Secondary Error Capabilities and Control Register The secondary error capabilities and control register allows the system to monitor and control the secondary advanced error reporting capabilities. See Table 5-11 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 5.14 Secondary Header Log Register The secondary header log register stores the transaction address and command for the PCI bus cycle that led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register bits 127:96. See Table 5-12 for a complete description of the register contents.
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XIO2001 www.ti.com 6 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Memory-Mapped TI Proprietary Register Space The programming model of the memory-mapped TI proprietary register space is unique to this device. All bits marked with a ☆ are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset. All bits marked with a (2) are reset by a PCI Express reset (PERST), a GRST or the internally-generated power-on reset.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 6.2 www.ti.com Revision ID Register The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value 00h identifies the revision as the initial layout. Device control memory window register offset: 01h Register type: Read-only Default value: 00h BIT NUMBER RESET STATE 6.
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XIO2001 www.ti.com 6.4 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL). The default value at power up depends on the state of the GPIO terminals as they default to generalpurpose inputs.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 6.5 www.ti.com Serial-Bus Data Register The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this register prior to writing the serial-bus slave address register that initiates the bus cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and status register (offset 47h, see Section 6.8) is cleared.
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XIO2001 www.ti.com 6.8 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial-bus. This register is an alias for the serial-bus control and status register in the PCI header (offset B3h, see Section 4.58). See Table 6-5 for a complete description of the register contents.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 6.9 www.ti.com Serial IRQ Mode Control Register This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode control register in the classic PCI configuration space (offset E0h, see Section 4.72). See Table 446 for a complete description of the register contents.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 6-7.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 6-7. Serial IRQ Edge Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION IRQ 3 edge mode 3 (1) IRQ3_MODE RW 0 = Edge mode (default) 1 = Level mode IRQ 2 edge mode 2 (1) IRQ2_MODE RW 0 = Edge mode (default) 1 = Level mode IRQ 1 edge mode 1 (1) IRQ1_MODE RW 0 = Edge mode (default) 1 = Level mode IRQ 0 edge mode 0 (1) IRQ0_MODE RW 0 = Edge mode (default) 1 = Level mode 6.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 6-8. Serial IRQ Status Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted. 12 (1) IRQ12 RCU 0 = Deasserted 1 = Asserted IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted. 11 (1) IRQ11 RCU 0 = Deasserted 1 = Asserted IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 6-8. Serial IRQ Status Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted. 0 (2) IRQ0 RCU 0 = Deasserted 1 = Asserted 6.12 Pre-Fetch Agent Request Limits Register This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Table 6-9. Pre-Fetch Agent Request Limits Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION Request Length Limit. Determines the number of bytes in the thread that the pre-fetch agent will read for that thread. 0000 = 64 bytes 0001 = 128 bytes 0010 = 256 bytes 3:0 PFA_REQ_LENGT H_LIMIT RW 0011 = 512 bytes 0100 = 1 Kbytes 0101 = 2 Kbytes 0110 = 4 Kbytes 0111 = 8 Kbytes 1000:1111 = Reserved 6.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com Table 6-11. Cache Timer Lower Limit Register Description BIT FIELD NAME 15:12 RSVD 11:0 (1) CACHE_TIMER _LOWER_LIMIT (1) ACCESS R DESCRIPTION Reserved. Returns 0h when read. RW Minimum number of clock cycles that must have passed without a read hit on the completion data buffer before the "cache miss limit" check can be triggered.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 7 Electrical Characteristics 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted) VDD_33 (1) Supply voltage range VDD_15 PCI –0.5 to 3.6 V V –0.5 to PCIR + 0.5 V –0.6 to 0.6 V PCI Express REFCLK (single-ended) –0.5 to VDD_33 + 0.5 V PCI Express REFCLK (differential) –0.5 to VDD_15 + 0.5 V Miscellaneous 3.3-V IO –0.5 to VDD_33 + 0.5 V PCI –0.5 to VDD_33 + 0.5 V PCI Express (TX) –0.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 7.3 www.ti.com Nominal Power Consumption DEVICES No downstream PCI devices POWER STATE (1) VOLTS AMPERES WATTS 1.5 0.147 0.221 0.062 0.205 0.209 0.426 0.148 0.222 0.077 0.254 0.225 0.476 0.157 0.236 0.165 0.545 0.322 0.780 1.65 0.168 0.277 3.6 0.188 0.677 0.356 0.954 D0 idle 3.3 Totals: One downstream PCI device 1.5 D0 idle 3.3 Totals: One downstream PCI device 1.5 D0 active 3.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 PCI Express Differential Transmitter Output Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS VTX-CM-AC-P (7) TX AC common mode voltage TXP, TXN 20 mV ITX-SHORT Transmitter short-circuit current limit TXP, TXN 90 mA The total current transmitter can supply when shorted to ground. VTX-DC-CM Transmitter DC common-mode voltage TXP, TXN 0 3.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com PCI Express Differential Receiver Input Ranges (continued) PARAMETER BWRX-PLL-LO-3DB (4) Minimum Rx PLL for 3 dB peaking TERMINALS MIN RXP, RXN 1.5 NOM MAX UNIT COMMENTS MHz Second order PLL jitter transfer bounding function. mV VRX-CM-AC-P = RMS(|VRXP + VRXN|/2 – VRX-CM-DC) VRX-CM-DC = DC(avg) of |VRXP + VRXN|/2.
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XIO2001 www.ti.com 7.7 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 PCI Bus Electrical Characteristics (1) over recommended operating conditions PARAMETER OPERATION TEST CONDITIONS MIN MAX 0.5 × VDD_33 PCIR + 0.5 2.0 PCIR + 0.5 PCIR = 3.3 V –0.5 0.3 × VDD_33 PCIR = 5 V –0.5 0.8 PCIR = 3.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com PCI Bus Timing Requirements (1) 7.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 ZAJ Thermal Characteristics(1) (continued) PARAMETER TJ Virtual junction temperature 7.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 www.ti.com 7.13 Parameter Measurement Information PCI Bus LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 30/50 12 - 12 0 3 30/50 12 - 12 1.5 30/50 12 - 12 ‡ tpd IOL Test Point From Output Under Test VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD - VOL = 50 Ω, where V OL = 0.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 CLK tw PRST tsu Figure 7-3. PRST Timing Waveforms CLK 1.5 V tpd PCI Output tpd 1.5 V Valid ton PCI Input toff Valid tsu th Figure 7-4.
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XIO2001 SCPS212G – MAY 2009 – REVISED DECEMBER 2012 VC 124 www.ti.
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XIO2001 www.ti.com SCPS212G – MAY 2009 – REVISED DECEMBER 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (May 2012) to Revision G • • • • Page Changed External Parts for CLKRUN_EN to include pulldown resistor ..................................................... Deleted Note from CLKRUN_EN terminal's description .......................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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