XIO2213B XIO2213B PCI Express™ TO 1394b OHCI WITH 3-PORT PHY Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Contents 1 ...................................................................................................................... ....................................................................................................... Overview .......................................................................................................................... 2.1 Related Documents ..........................................................
XIO2213B www.ti.com 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 4.56 4.57 4.58 4.59 4.60 4.61 4.62 4.63 4.64 4.65 4.66 4.67 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Secondary Latency Timer Register ..................................................................................... I/O Base Register ............................................
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.68 4.69 4.70 4.71 4.72 4.73 4.74 4.75 5 6 4 .................................................................................... 96 ................................................................... 109 Device Control Map ID Register ....................................................................................... Revision ID Register .....................................................................................................
XIO2213B www.ti.com 7.21 7.22 7.23 8 PCI Miscellaneous Configuration Register ........................................................................... 125 Link Enhancement Control Register ................................................................................... 128 Subsystem Access Register ............................................................................................ 130 1394 OHCI Memory-Mapped Register Space 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 9.3 9.4 9.5 10 11 Isochronous Receive Digital Video Enhancement Registers ...................................................... 175 Link Enhancement Control Registers ................................................................................. 176 Timestamp Offset Registers ............................................................................................ 178 Physical Layer (PHY) Section 10.1 10.2 .....................................
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 List of Figures 3-1 XIO2213B Block Diagram ....................................................................................................... 31 3-2 Power-Up Sequence ............................................................................................................. 32 3-3 Power-Down Sequence 3-4 PCIe Assert_INTA Message ....................................................................................................
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com List of Tables 2-1 7 × 7 Terminals Sorted By Ball Number....................................................................................... 16 2-2 7 × 7 Terminals Sorted Alphanumerically ..................................................................................... 18 2-3 12 × 12 Terminals Sorted By Ball Number....................................................................................
XIO2213B www.ti.com 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 ........................................................................................ ............................................................................................. Link Status Register Description .............
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7-17 7-18 7-19 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 10-5 10-6 10 www.ti.com ................................................................................. .......................................................................... Subsystem Access Register Description .....................
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 ...................................................................... ................................................................ ...........................................................................................
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com XIO2213B PCI Express™ TO 1394b OHCI WITH 3-PORT PHY Check for Samples: XIO2213B 1 Introduction 1.1 XIO2213B Features 123 • Full ×1 PCI Express™ (PCIe) Throughput • Fully Compliant With PCI Express Base Specification, Revision 1.
XIO2213B www.ti.com 2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Overview The Texas Instruments XIO2213B is a single-function PCI Express™ (PCIe) to PCI local bus translation bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer controller with a 3-port 1394b physical layer (PHY). When the XIO2213B is properly configured, this solution provides full PCIe and 1394b functionality and performance.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com To ensure that the XIO2213B conforms to IEEE Std 1394b-2002, the BMODE terminal must be asserted. The BMODE terminal does not select the cable-interface mode of operation. BMODE selects the internal PHY-section/LLC-section interface mode of operation and affects the arbitration modes on the cable. BMODE must be pulled high during normal operation.
XIO2213B www.ti.com 2.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Documents Conventions Throughout this data manual, several conventions are used to convey information. These conventions are: • To identify a binary number or field, a lower-case b follows the numbers. For example, 000b is a 3-bit binary field. • To identify a hexadecimal number or field, a lower-case h follows the numbers. For example, 8AFh is a 12-bit hexadecimal field.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 2.4 www.ti.com Terminal Assignments The XIO2213B is packaged in a 168-ball BGA (ZAJ) and a 167-ball PBGA (ZAY). For the ZAJ package Table 2-1 lists the terminals sorted by ball number. Table 2-2 lists the terminals in alphanumerical order. For the ZAY packageTable 2-3 lists the terminals sorted by ball number. Table 2-4 lists the terminals in alphanumerical order. Table 2-1. 7 × 7 Terminals Sorted By Ball Number (continued) Table 2-1.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-1. 7 × 7 Terminals Sorted By Ball Number (continued) BALL NO. TERMINAL NAME Table 2-1. 7 × 7 Terminals Sorted By Ball Number (continued) BALL NO. TERMINAL NAME G13 TPB1+ L01 D6 H01 D0 L02 GPIO2 H02 D1 L03 VDD_33 H03 VDD_15 L04 GPIO3 H04 GND L05 GPIO7 H05 GND L06 VDD_15 H06 GND L07 GND H07 GND L08 VDD_33 H08 GND L09 CYCLEOUT H09 VDD_15 L10 RSVD H10 AVDD_3.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-2. 7 × 7 Terminals Sorted Alphanumerically Table 2-2. 7 × 7 Terminals Sorted Alphanumerically (continued) BALL NO. BALL NO. TERMINAL NAME TERMINAL NAME J07 GND E10 AVDD_3.3 F10 AVDD_3.3 J08 GND AVDD_3.3 K07 GND AVDD_3.3 L07 GND AVDD_3.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-2. 7 × 7 Terminals Sorted Alphanumerically (continued) Table 2-2. 7 × 7 Terminals Sorted Alphanumerically (continued) BALL NO. BALL NO.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 2-3. 12 × 12 Terminals Sorted By Ball Number BALL NO. BALL NO. TERMINAL NAME A01 REFCLK+ E03 A02 CNA E06 GND RXN E07 GND RXP E08 PC1 BMODE E09 PC0 VREG_PD E10 AVDD_3.3 VSS E12 RSVD TXN E13 TPBIAS2 TXP E14 TPB2– VDDA_33 F01 PCLK_P PC2 F02 LREQ_L REF1_PCIE F03 DVDD_CORE REF0_PCIE F05 VSSA VSS F06 GND REFCLK– F07 GND B02 TESTM F08 GND B03 PD F09 GND B04 PHY_RESET F10 AVDD_3.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-3. 12 × 12 Terminals Sorted By Ball Number (continued) BALL NO. TERMINAL NAME Table 2-3. 12 × 12 Terminals Sorted By Ball Number (continued) BALL NO. TERMINAL NAME J07 GND M10 AVDD_3.3 J08 GND M11 RSVD J09 AVDD_3.3 M12 RSVD J10 VDD_33 M13 RSVD J12 CLKREQ M14 TPB0+ J13 SCL N01 R0 J14 TPB1– N02 GPIO1 K01 D2 N03 GPIO3 K02 D1 N04 GPIO4 K03 DVDD_3.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 2-4. 12 × 12 Terminals Sorted Alphanumerically TERMINAL NAME Table 2-4. 12 × 12 Terminals Sorted Alphanumerically (continued) TERMINAL NAME BALL NO. BALL NO. AVDD_3.3 E10 GND AVDD_3.3 F10 GND J09 GND J08 AVDD_3.3 K09 GND K05 AVDD_3.3 M10 GND K06 AVDD_3.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-4. 12 × 12 Terminals Sorted Alphanumerically (continued) TERMINAL NAME RSVD Table 2-4. 12 × 12 Terminals Sorted Alphanumerically (continued) BALL NO. TERMINAL NAME BALL NO.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 2.5 www.ti.com Terminal Descriptions The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-5. Power-Supply Terminals BALL NO. I/O TYPE EXTERNAL PARTS C07 H03 H09 J03 J09 L06 PWR Bypass capacitors B10 B09 B07 B05 B04 B05 C04 C05 PWR Filter E03 M05 J10 H10 G10 D10 K03 K08 L03 L08 PWR Bypass capacitors B12 C09 VDDA_33 C03 A10 A01 C08 PWR Filter 3.3-V analog power for the link. This supply terminal is separated from the other power terminals internal to the device to provide noise isolation.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 2-6. Ground Terminals BALL NO. SIGNAL ZAY PACKAGE ZAJ PACKAGE I/O TYPE DESCRIPTION VSS A07 A14 E07 E08 GND Digital ground for link VSSA B06 C10 F05 D04 D07 E09 GND Analog ground for link VSSA_PCIE C04 C05 C06 C07 C06 D05 D06 E06 GND Analog ground for PCIe function PLLGND N05 N04 GND PLL circuit ground. This terminal must be tied to the lowimpedance circuit-board ground plane. GND Ground.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-9. 1394 Terminals BALL NO. SIGNAL I/O TYPE DESCRIPTION ZAY PACKAGE ZAJ PACKAGE CNA A02 A02 I/O CPS P12 N09 I Cable power status. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. If CPS is not used to detect cable power, this terminal must be connected to VSSA.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 2-9. 1394 Terminals (continued) BALL NO. SIGNAL I/O TYPE DESCRIPTION ZAY PACKAGE ZAJ PACKAGE PINT_P D03 E03 O PHY-section interrupt. PINT_P is a serial input to the LLC section from the PHY section that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PINT_P is synchronous to PCLK_P. This terminal must be connected to the PINT_L input of the LLC section.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 2-10. Reserved Terminals BALL NO. SIGNAL ZAY PACKAGE ZAJ PACKAGE I/O TYPE RSVD E12 F12 F13 K12 L12 L13 M11 M12 M13 N10 N11 N12 N13 P03 P10 P11 D11 E11 F12 J11 K10 K11 K12 L10 L11 L12 M05 M11 M12 N11 N12 N13 I/O RSVD D12 D13 G12 M08 C10 D12 F11 M09 I DESCRIPTION Reserved, do not connect to external signals. Must be connected to VSS. Table 2-11. Miscellaneous Terminals BALL NO.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 2-11. Miscellaneous Terminals (continued) BALL NO. SIGNAL ZAY PACKAGE ZAJ PACKAGE H12 H11 SDA I/O TYPE I/O DESCRIPTION Serial-bus data. This signal is used as serial bus data when a pullup is detected on SDA or when the SBDETECT bit is set in the serial bus control and status register. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating. BMODE A05 B06 I Beta mode.
XIO2213B www.ti.com 3 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Feature/Protocol Descriptions This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified block diagram of the basic architecture of the PCIe to PCI bridge with 1394b OHCI and 3-port PHY. The top of the diagram is the PCIe interface, and the 1394b OHCI with 3-port PHY is located at the bottom of the diagram.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 3.1.1 www.ti.com Power-Up Sequence 1. 2. 3. 4. Assert PERST to the device. Apply 1.5-V and 3.3-V voltages. Apply a stable PCIe reference clock. To meet PCIe specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: – Wait a minimum of 100 s after applying a stable PCIe reference clock. The 100-s limit satisfies the requirement for stable device clocks by the deassertion of PERST.
XIO2213B www.ti.com 3.1.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Power-Down Sequence 1. Assert PERST to the device. 2. Remove the reference clock. 3. Remove 3.3-V and 1.5-V voltages. See the power-down sequencing diagram in Figure 3-3. If the VDD_33_AUX terminal is to remain powered after a system shutdown, the bridge power-down sequence is the same as shown in Figure 3-3. VDD_15 and VDDA_15 VDD_33 and VDDA_33 REFCLK PERST Figure 3-3.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 3.2 www.ti.com XIO2213B Reset Features There are five XIO2213B reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCIe hot reset or setting a configuration register bit. Table 3-1 identifies these reset sources and describes how the XIO2213B responds to each reset. Table 3-1.
XIO2213B www.ti.com 3.3 3.3.1 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 PCI Express (PCIe) Interface External Reference Clock The XIO2213B requires either a differential, 100-MHz common clock reference or a single-ended, 125MHz clock reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for frequency tolerance, spread-spectrum clocking, and signal electrical characteristics.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 3.3.4 www.ti.com PCIe Message Transactions PCIe messages are both initiated and received by the bridge. Table 3-3 outlines message support within the bridge. Table 3-3.
XIO2213B www.ti.com 3.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 PCI Interrupt Conversion to PCIe Messages The bridge converts interrupts from the PCI bus sideband interrupt signals to PCIe interrupt messages. Since the 1394a OHCI only generates INTA interrupts, only PCIe INTA messages are generated by the bridge. PCIe Assert_INTA messages are generated when the 1394a OHCI signals an INTA interrupt.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 3.5 www.ti.com Two-Wire Serial-Bus Interface The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific register defaults from an external EEPROM. The serial-bus interface signals are SCL and SDA. 3.5.1 Serial-Bus Interface Implementation To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal.
XIO2213B www.ti.com 3.5.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Serial-Bus Interface Protocol All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state (see Figure 3-7).
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com S Data Byte Word Address Slave Address b6 b5 b4 b3 b2 b1 b0 0 A b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave Acknowledgement S/P = Start/Stop Condition Figure 3-9. Serial-Bus Protocol Byte Write Figure 3-10 shows a single-byte read. The bridge issues a start condition and sends the 7-bit slave device address, and the R/W command bit is equal to 0b (write).
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three previous serial-bus protocol figures show the PROT_SEL bit default (logic low). When this control bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol. This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM devices. 3.5.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 3-4.
XIO2213B www.ti.com 3.5.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Accessing Serial-Bus Devices Through Softwaree The bridge provides a programming mechanism to control serial-bus devices through system software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3-5 lists the registers that program a serial-bus device through software. Table 3-5.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 3.8 www.ti.com General-Purpose I/O (GPIO) Interface Up to eight GPIO terminals are provided for system customization. These GPIO terminals are 3.3-V tolerant. The exact number of GPIO terminals varies based on implementing the clock-run, power-override, and serial EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three shared functions are enabled, the associated GPIO terminal is disabled.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 The link power management (LPM) state machine manages active-state power by monitoring the PCIe transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum time required by the PCI Express Specification, the LPM state machine transitions the link to either the L0s or L1 state.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 3.11 1394b OHCI Controller Functionality 3.11.1 1394b OHCI Power Management The 1394b OHCI controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 3-8. 1394 OHCI Memory Command Options PCI COMMAND C/BE3C/BE0 OHCI MASTER FUNCTION DMA read from memory Memory read 0110 Memory write 0111 DMA write to memory Memory read multiple 1100 DMA read from memory Memory read line 1110 DMA read from memory Memory write and invalidate 1111 DMA write to memory 3.11.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4 www.ti.com Classic PCI Configuration Space The programming model of the XIO2213B PCIe to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header. Sticky bits are reset by a global reset (GRST) or the internally-generated power-on reset. EEPROM loadable bits are reset by a PCIe reset (PERST), GRST, or the internally-generated power-on reset.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 4-1.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 4-2. Command Register Description BIT 15:11 FIELD NAME ACCESS DESCRIPTION RSVD R Reserved. Returns 00000b when read. 10 INT_DISABLE R INTx disable. This bit enables device specific interrupts. Since the bridge does not generate any internal interrupts, this bit is read-only 0b. 9 FBB_ENB R Fast back-to-back enable. The bridge does not generate fast back-to-back transactions; therefore, this bit returns 0b when read.
XIO2213B www.ti.com 4.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Status Register The status register provides information about the PCIe interface to the system. See Table 4-3 for a complete description of the register contents. PCI register offset: 06h Register type: Read only, Read/Clear Default value: 0010h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 Table 4-3.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.5 www.ti.com Class Code and Revision ID Register This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI to PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte (00h).
XIO2213B www.ti.com 4.8 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Header Type Register This read-only register indicates that this function has a type 1 PCI header. Bit 7 of this register is 0b, indicating that the bridge is a single-function device. PCI register offset: 0Eh Register type: Read only Default value: 01h BIT NUMBER RESET STATE 4.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.11 Scratchpad RAM Base Address This register is used to program the memory address used to access the embedded scratchpad RAM.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.14 Subordinate Bus Number Register This read/write register specifies the bus number of the highest-number PCI bus segment that is downstream of the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this register must always be equal to the secondary bus number register (offset 19h, see Section 4.13). The bridge uses this register to determine how to respond to a type 1 configuration transaction.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.17 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See Table 4-8 for a complete description of the register contents. PCI register offset: 1Dh Register type: Read only, Read/Write Default value: 01h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Table 4-8.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.18 Secondary Status Register The secondary status register provides information about the PCI bus interface. See Table 4-9 for a complete description of the register contents. PCI register offset: 1Eh Register type: Read only, Read/Clear Default value: 02X0h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 x 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-9.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.19 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4-10 for a complete description of the register contents. PCI register offset: 20h Register type: Read only, Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-10.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.21 Prefetchable Memory Base Register This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4-12 for a complete description of the register contents. PCI register offset: 24h Register type: Read only, Read/Write Default value: 0001h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Table 4-12.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.23 Prefetchable Base Upper 32 Bits Register This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 414 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.25 I/O Base Upper 16 Bits Register This read/write register specifies the upper 16 bits of the I/O base register. See Table 4-16 for a complete description of the register contents. PCI register offset: 30h Register type: Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-16.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.27 Capabilities Pointer Register This read-only register provides a pointer into the PCI configuration header where the PCI power management block resides. Since the PCI power-management registers begin at 50h, this register is hardwired to 50h. PCI register offset: 34h Register type: Read only Default value: 50h BIT NUMBER RESET STATE 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 0 4.
XIO2213B www.ti.com 4.30 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Bridge Control Register The bridge control register provides extensions to the command register that are specific to a bridge. See Table 4-18 for a complete description of the register contents. PCI register offset: 3Eh Register type: Read only, Read/Write, Read/Clear Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-18.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 4-18. Bridge Control Register Description (continued) BIT 5 FIELD NAME MAM ACCESS RW DESCRIPTION Master abort mode. This bit controls the behavior of the bridge when it receives a master abort or an unsupported request. 0 = Do not report master aborts. Returns FFFF FFFFh on reads and discard data on writes (default). 1 = Respond with an unsupported request on PCIe when a master abort is received on PCI.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 4-18. Bridge Control Register Description (continued) BIT 0 FIELD NAME ACCESS DESCRIPTION RW Parity error response enable. Controls the bridge's response to data, uncorrectable address, and attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning, from conventional PCI to PCIe on an uncorrectable conventional PCI data error, regardless of the setting of this bit.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.33 Power Management Capabilities Register This read-only register indicates the capabilities of the bridge related to PCI power management. See Table 4-19 for a complete description of the register contents. PCI register offset: 52h Register type: Read only Default value: 0603h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 1 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 1 Table 4-19.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.34 Power Management Control/Status Register This register determines and changes the current power state of the bridge. No internal reset is generated when transitioning from the D3hot state to the D0 state. See Table 4-20 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.35 Power Management Bridge Support Extension Register This read-only register indicates to host software what the state of the secondary bus will be when the bridge is placed in D3. See Table 4-21 for a complete description of the register contents. PCI register offset: 56h Register type: Read only Default value: 40h BIT NUMBER RESET STATE 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-21.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.38 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 80h pointing to the subsystem ID capabilities registers. PCI register offset: 61h Register type: Read only Default value: 80h BIT NUMBER RESET STATE 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.39 MSI Message Control Register This register controls the sending of MSI messages.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.40 MSI Message Lower Address Register This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is detected. See Table 4-23 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.42 MSI Message Data Register This register contains the data that software programmed the bridge to send when it send a MSI message. See Table 4-24 for a complete description of the register contents. PCI register offset: 6Ch Register type: Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-24.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.45 Subsystem Vendor ID Register This register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem alias register. This register shall only be reset by a fundamental reset (FRST).
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.49 PCI Express Capabilities Register This read-only register indicates the capabilities of the bridge related to PCIe. See Table 4-25 for a complete description of the register contents. PCI register offset: 92h Register type: Read only Default value: 0071h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 1 5 1 4 1 3 0 2 0 1 0 0 1 Table 4-25.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.50 Device Capabilities Register This register indicates the device-specific capabilities of the bridge. See Table 4-26 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.51 Device Control Register The device control register controls PCIe device-specific meters. See Table 4-27 for a complete description of the register contents. PCI register offset: 98h Register type: Read only, Read/Write Default value: 2800h BIT NUMBER RESET STATE 15 0 14 0 13 1 12 0 11 1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-27.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 4-27. Device Control Register Description (continued) BIT 2 FIELD NAME ACCESS FERE DESCRIPTION RW Fatal error reporting enable. If this bit is set, the bridge is enabled to send ERR_FATAL messages to the root complex when a system error event occurs. 0 = Do not report fatal errors to the root complex (default) 1 = Report fatal errors to the root complex 1 NFERE RW Nonfatal error reporting enable.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.53 Link Capabilities Register The link capabilities register indicates the link-specific capabilities of the bridge. See Table 4-29 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.54 Link Control Register The link control register controls link-specific behavior. See Table 4-30 for a complete description of the register contents. PCI register offset: A0h Register type: Read only, Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-30.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.55 Link Status Register The link status register indicates the current state of the PCIe link. See Table 4-31 for a complete description of the register contents. PCI register offset: A2h Register type: Read only Default value: X011h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 x 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 1 Table 4-31.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 BIT NUMBER RESET STATE 7 0 6 0 www.ti.com 5 0 4 0 3 0 2 0 1 0 0 0 4.58 Serial-Bus Slave Address Register The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle on the serial interface. See Table 4-32 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.59 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial bus. See Table 4-33 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.60 GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). See Table 4-34 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.61 GPIO Data Register This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.62 Control and Diagnostic Register 0 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4-36 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 4-36. Control and Diagnostic Register 0 Description (continued) BIT 6(1) FIELD NAME PREFETCH_4X ACCESS RW DESCRIPTION Prefetch 4× enable 0 = Bridge prefetches up to two cache lines, as defined in the cache line size register (offset 0Ch, see Section 7.6) for upstream memory read multiple (MRM) transactions (default). 1 = Bridge prefetches up to four cache lines, as defined in the cache line size register (offset 0Ch, see Section 7.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.63 Control and Diagnostic Register 1 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4-37 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.64 PHY Control and Diagnostic Register 2 The contents of this register are used for monitoring status and controlling behavior of the PHY macro for diagnostic purposes. See Table 4-38 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.65 Subsystem Access Register The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 84h and 86h. See Table 4-39 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 4-40. General Control Register Description BIT 31:30 (1) FIELD NAME CFG_RETRY_ CNTR ACCESS RW DESCRIPTION Configuration retry counter. Configures the amount of time that a configuration request must be retried on the secondary PCI bus before it may be completed with configuration retry status on the PCIe side.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 4-40. General Control Register Description (continued) BIT FIELD NAME ACCESS 19 (1) READ_ PREFETCH_ DIS RW DESCRIPTION Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.67 TI Proprietary Register This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST. PCI register offset: D8h Register type: Read only, Read/Write Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.70 Arbiter Control Register The arbiter control register controls the device's internal arbiter. The arbitration scheme used is a twotier rotational arbitration. The device is the only secondary bus master that defaults to the higherpriority arbitration tier. See Table 4-41 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.71 Arbiter Request Mask Register The arbiter request mask register enables and disables support for requests from specific masters on the secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an arbiter time-out. See Table 4-42 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 4.72 Arbiter Time-Out Status Register The arbiter time-out status register contains the status of each request (request 50) time-out. The time-out status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See Table 4-43 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 4.73 TI Proprietary Register This read/write TI proprietary register is located at offset E0h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST. PCI register offset: E0h Register type: Read only, Read/Write Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 5 www.ti.com PCIe Extended Configuration Space The programming model of the PCIe extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCIe extended configuration map uses the PCIe advanced error reporting capability and PCIe virtual channel (VC) capability headers.
XIO2213B www.ti.com 5.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Next Capability Offset/Capability Version Register This read-only register identifies the next location in the PCIe extended capabilities link list. The upper 12 bits in this register shall be 000h, indicating that the advanced error reporting capability is the last capability in the linked list. The least significant four bits identify the revision of the current capability block as 1h.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 5.4 www.ti.com Uncorrectable Error Mask Register The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-3 for a complete description of the register contents.
XIO2213B www.ti.com 5.5 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5-4 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 5-4. Uncorrectable Error Severity Register Description (continued) BIT 0 100 FIELD NAME RSVD ACCESS R DESCRIPTION Reserved. Returns 1h when read.
XIO2213B www.ti.com 5.6 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Correctable Error Status Register The correctable error status register reports the status of individual errors as they occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5-5 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 5.7 www.ti.com Correctable Error Mask Register The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-6 for a complete description of the register contents.
XIO2213B www.ti.com 5.8 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Advanced Error Capabilities and Control Register The advanced error capabilities and control register allows the system to monitor and control the advanced error reporting capabilities. See Table 5-7 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 5.10 Secondary Uncorrectable Error Status Register The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5-8 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 5.11 Secondary Uncorrectable Error Mask Register The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-9 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 5.12 Secondary Uncorrectable Error Severity The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5-10 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 5.13 Secondary Error Capabilities and Control Register The secondary error capabilities and control register allows the system to monitor and control the secondary advanced error reporting capabilities. See Table 5-11 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 5.14 Secondary Header Log Register The secondary header log register stores the transaction address and command for the PCI bus cycle that led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register bits 127:96. See Table 5-12 for a complete description of the register contents.
XIO2213B www.ti.com 6 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Memory-Mapped TI Proprietary Register Space The programming model of the memory-mapped TI proprietary register space is unique to this device. These custom registers are specifically designed to provide enhanced features associated with upstream isochronous applications. Sticky bits are reset by a fundamental reset (FRST). Table 6-1.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 6.2 www.ti.com Revision ID Register Device control memory window register offset: 01h Register type: Read only Default value: 00h BIT NUMBER RESET STATE 6.3 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions.
XIO2213B www.ti.com 6.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 GPIO Data Register This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 6.5 www.ti.com Serial-Bus Data Register The serial-bus data register is used to read and write data on the serial-bus interface. When writing data to the serial bus, this register must be written before writing to the serial-bus address register to initiate the cycle. When reading data from the serial bus, this register will contain the data read after the REQBUSY (bit 5 serial-bus control register) bit is cleared.
XIO2213B www.ti.com 6.8 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Serial-Bus Control and Status Register The serial-bus control and status register is used to control the behavior of the serial-bus interface. This register also provides status information about the state of the serial bus. This register is an alias for the serial-bus control and status register in the PCI header.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7 www.ti.com 1394 OHCI PCI Configuration Space The 1394 OHCI core is integrated as a PCI device behind the PCIe to PCI bridge. The configuration header for the 1394b OHCI portion of the design is compliant with the PCI specification as a standard header. Table 7-1 shows the configuration header that includes both the predefined portion of the configuration space and the user-definable registers.
XIO2213B www.ti.com 7.1 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the OHCI controller. The vendor ID assigned to TI is 104Ch. PCI register offset: 00h Register type: Read only Default value: 104Ch BIT NUMBER RESET STATE 7.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.3 www.ti.com Command Register The command register provides control over the 1394b OHCI function interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as shown in the following bit descriptions. See Table 7-2 for a complete description of the register contents.
XIO2213B www.ti.com 7.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Status Register The status register provides status over the 1394b OHCI controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as shown in the following bit descriptions. See Table 7-3 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.5 www.ti.com Class Code and Revision ID Registers The class code and revision ID registers categorize the 1394b OHCI controller as a serial bus controller (0Ch), controlling an IEEE Std 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7-4 for a complete description of the register contents.
XIO2213B www.ti.com 7.7 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Header Type and BIST Registers The header type and built-in self-test (BIST) registers indicate the OHCI controller PCI header type and no built-in self-test. See Table 7-6 for a complete description of the register contents. PCI register offset: 0Eh Register type: Read only Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 7-6.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.9 www.ti.com TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memorymapped TI extension registers. When the BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7-8 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.11 CIS Pointer Register The CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0000 0000h when read. PCI register offset: 28h Register type: Read only Default value: 0000 0000h BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 7.13 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. The OHCI controller configuration header double words at offsets 44h and 48h provide the power-management registers. This register is read only and returns 44h when read.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.15 Minimum Grant and Minimum Latency Registers The minimum grant and minimum latency registers communicate to the system the desired setting of bits 15–8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, the contents of these registers are loaded through the serial EEPROM interface.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 7.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer registers identify the linked-list capability item and provide a pointer to the next capability item. See Table 7-13 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 7.19 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI powermanagement function. This register is not affected by the internally-generated reset caused by the transition from the D3hot to D0 state. See Table 7-15 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 (1) 126 www.ti.com BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 (1) 1 6 0 5 0 4 1 3 0 2 0 1 0 0 0 These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 7-17. PCI Miscellaneous Configuration Register BIT 31-16 15 14-12 FIELD NAME TYPE DESCRIPTION RSVD R Reserved. Bits 31-16 return 0000h when read. PME_D3COLD R PME support from D3cold. The 1394a OHCI core does not support PME generation from D3cold. Therefore, this bit is tied to 0b. RSVD R Reserved. Bits 14-12 return 000b when read. 11 PCI2_3_EN R PCI 2.3 enable. The 1394 OHCI core always conforms to the PCI 2.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 7.22 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1b, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2, Host Controller Control Register) is set to 1.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 7-18. Link Enhancement Control Register Description BIT FIELD NAME TYPE RSVD 15(1) dis_at_pipeline RW Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value for this bit is 0b. 14(1) ENAB_DRAFT RW Enable OHCI 1.2 draft features. When this bit is set, it enables some features beyond the OHCI 1.1 specification. Specifically, this enables HCControl.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 7.23 Subsystem Access Register Write access to the subsystem access register identically updates the subsystem ID registers to OHCILynx. The system ID value written to this register may also be read back from this register. See Table 719 for a complete description of the register contents.
XIO2213B www.ti.com 8 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 1394 OHCI Memory-Mapped Register Space The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the IEEE Std 1394 link function. This section provides the register interface and bit descriptions.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 8-1.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-1.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.1 www.ti.com OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8-2 for a complete description of the register contents.
XIO2213B www.ti.com 8.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1b. See Table 8-3 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.3 www.ti.com Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8-4 for a complete description of the register contents.
XIO2213B www.ti.com 8.5 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 CSR Compare Register The CSR compare register accesses the bus-management CSR registers from the host through compareswap operations. This register contains the data to be compared with the existing value of the CSR resource.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.7 www.ti.com Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8-6 for a complete description of the register contents.
XIO2213B www.ti.com 8.9 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8-7 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0000 0000h on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, the contents of this register are loaded through the serial EEPROM interface.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 8-8 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 8-10 for a complete description of the register contents.
XIO2213B www.ti.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 8-11. Host Controller Control Register Description BIT 31 FIELD NAME BIBimageValid TYPE DESCRIPTION RSU When bit 31 is set to 1b, the physical response unit is enabled to respond to block read requests to host configuration ROM and to the mechanism for atomically updating configuration ROM. Software creates a valid image of the bus_info_block in host configuration ROM before setting this bit.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2K-byte-aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31-11 are read/write accessible. Bits 100 are reserved and return 000 0000 0000b when read.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set or clear register returns the content of the isochronous receive channel mask high register. See Table 8-13 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-13. Isochronous Receive Channel Mask High Register Description (continued) BIT 0 FIELD NAME isoChannel32 TYPE RSC DESCRIPTION When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 32.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 8-14 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-15. Interrupt Event Register Description BIT FIELD NAME TYPE R DESCRIPTION 31 RSVD 30 vendorSpecific RSC This vendor-specific interrupt event is reported when either of the general-purpose interrupts are asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT_3EN and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the PCI configuration space.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 8-15.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-16. Interrupt Mask Register Description (continued) BIT FIELD NAME TYPE DESCRIPTION 24 unrecoverableError RSC When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 11b, this unrecoverable-error interrupt mask enables interrupt generation.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a perchannel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 8-17.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a perchannel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 8-18.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus-management CSR register on a system (hardware) or software reset. See Table 8-20 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 8-22 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the controller. It contains controls for the receiver and cycle timer. See Table 8-23 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15-6) and the NodeNumber field (bits 5-0) is referred to as the node ID. See Table 8-24 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.33 PHY Control Register The PHY control register reads from or writes to a PHY register. See Table 8-25 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the controller is cycle master, this register is transmitted with the cycle start message. When the controller is not cycle master, this register is loaded with the data field in an incoming cycle start.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-27. Asynchronous Request Filter High Register Description BIT FIELD NAME TYPE 31 asynReqAllBuses RSC If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes are accepted. DESCRIPTION 30 asynReqResource62 RSC If bit 30 is set to 1b for local bus node number 62, asynchronous requests received by the controller from that node are accepted.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 8-27. Asynchronous Request Filter High Register Description (continued) BIT FIELD NAME TYPE 3 asynReqResource35 RSC If bit 3 is set to 1b for local bus node number 35, asynchronous requests received by the controller from that node are accepted. 2 asynReqResource34 RSC If bit 2 is set to 1b for local bus node number 34, asynchronous requests received by the controller from that node are accepted.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a pernode basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8-28 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 8-29. Physical Request Filter High Register Description BIT FIELD NAME TYPE 31 physReqAllBusses RSC If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes are accepted. Bit 31 is not cleared by a PRST.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-29. Physical Request Filter High Register Description (continued) BIT FIELD NAME TYPE 3 physReqResource 35 RSC If bit 3 is set to 1b for local bus node number 35, physical requests received by the controller from that node are handled through the physical request context.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, the node ID comparison is done again with this register.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8-31 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1b. See Table 8-32 for a complete description of the register contents.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). See Table 8-33 for a complete description of the register contents.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1b.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-34. Isochronous Receive Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 bufferFill RSC Buffer fill. When bit 31 is set to 1b, received packets are placed back to back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1b, this bit must also be set to 1b.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the controller accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1b.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 8-35. Isochronous Receive Context Match Register Description (continued) BIT FIELD NAME TYPE 5-0 channelNumber RW DESCRIPTION This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 9 www.ti.com 1394 OHCI Memory-Mapped TI Extension Register Space The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9-1 for the TI extension register listing. Table 9-1. TI Extension Register Map 9.
XIO2213B www.ti.com 9.2 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1).
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 9-2. Isochronous Receive Digital Video Enhancement Registers Description (continued) BIT FIELD NAME 4 CIP_Strip1 3-2 TYPE DESCRIPTION RSC When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 8.44) is cleared to 0b. RSVD R Reserved.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 9-3. Link Enhancement Control Registers Description (continued) BIT 13-12 FIELD NAME (2) atx_thresh TYPE DESCRIPTION RW This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the OHCI controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 9.5 www.ti.com Timestamp Offset Registers The value of these registers is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, ..., 7). These registers are programmed by software as appropriate. See Table 9-4 for a complete description of the register contents.
XIO2213B www.ti.com 10 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Physical Layer (PHY) Section The cable interface can follow either the IEEE Std 1394a-2000 protocol or the IEEE Std 1394b-2002 protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com When the XIO2213B PHY section is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 A reserved register or register field (marked as Reserved or RSVD in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 10-1.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 10-2. Base Register Field Description (continued) FIELD SIZE TYPE DESCRIPTION LCtrl 1 Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC section reported in the self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 10-2. Base Register Field Description (continued) FIELD SIZE TYPE Max_Legacy_S PD 3 Rd Maximum legacy path speed. This field holds the maximum speed capability of any legacy node (IEEE Std 1394a-2000 or 1394-1995 compliant) as indicated in the self-ID packets received during bus initialization. Encoding is the same as for the PHY_SPEED field (but limited to S400 maximum). DESCRIPTION BLINK 1 Rd Beta-mode link.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 10-4. Page 0 (Port Status) Register Field Description FIELD Astat SIZE TYPE 2 Rd DESCRIPTION TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as: Code 11 10 01 00 Arbitration Value Z 1 0 Invalid Bstat 2 Rd TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the Astat field. Ch 1 Rd Child/parent status.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Table 10-4. Page 0 (Port Status) Register Field Description (continued) SIZE TYPE DESCRIPTION Max_port_speed FIELD 3 Rd/Wr Maximum port speed. The maximum speed at which a port is allowed to operate in beta mode.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com Table 10-6. Page 1 (Vendor ID) Register Field Descriptions SIZE TYPE DESCRIPTION Compliance FIELD 8 Rd Compliance level. For the XIO2213B, this field is 02h, indicating compliance with the IEEE Std 1394b2002 specification. Vendor_ID 24 Rd Manufacturers organizationally unique identifier (OUI). For the XIO2213B, this field is 08 0028h (TI) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 The vendor dependent page provides access to the special control features of the XIO2213B, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10-7 shows the configuration of the vendor dependent page, and Table 10-8 shows the corresponding field descriptions. Table 10-7.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com 10.2.2 Power-Up Reset To ensure proper operation of the XIO2213B PHY section, the RESET terminal must be asserted low for a minimum of 2 ms from the time that DVDD, AVDD, and PLLVDD power reaches the minimum required supply voltage and the input clock is valid. If a fundamental-mode crystal is used rather than an oscillator, the start-up time parameter may be set to zero.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 10.2.4 Bus Reset It is recommended that whenever the user has a choice, the user should initiate a bus reset by writing to the initiate short bus reset (ISBR) bit (bit 1, PHY register 0101b). Care must be taken not to change the value of any of the other writeable bits in this register when the ISBR bit is written to.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 11 www.ti.com Electrical Characteristics Absolute Maximum Ratings (1) 11.1 over operating temperature range (unless otherwise noted) VALUE UNIT VSUP_33 Supply voltage range DVDD_33, VDDA_33, VDDA_33, VDDPLL_33, VDD_33_COMB, VDD_33_COMBIO 0.3 to 3.6 V VSUP_15 Supply voltage range VDD_15, VDDA_15, VPP, VDDPL L, VDD_15_COMB 0.5 to 1.65 V VCORE_195 Supply voltage range PLLVDD_CORE, DVDD_CORE 0.5 to 2.
XIO2213B www.ti.com SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Recommended Operating Conditions (continued) OPERATION θJB Junction-to-board thermal resistance ΨJT Junction-to-top of package ΨJB Junction-to-board 11.3 MIN EIA/JESD 51-8 ZAY NOM MAX UNIT 35 °C/W EIA/JESD 51-8 ZAJ 27 °C/W EIA/JESD 51-2 ZAY 0.1 °C/W EIA/JESD 51-2 ZAJ 0.13 °C/W EIS/JESD 51-6 ZAY 29.7 °C/W EIS/JESD 51-6 ZAJ 22.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 www.ti.com PCIe Differential Transmitter Output Ranges (continued) TXP and TXN PARAMETER MIN UNIT COMMENTS UI UI Maximum time to meet all TX specifications when transitioning from electrical idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving electrical idle. 10 dB Measured over 50 MHz to 1.25 GHz (5) 6 dB Measured over 50 MHz to 1.
XIO2213B www.ti.com 11.4 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 PCIe Differential Receiver Input Ranges RXP and RXN PARAMETER MIN UI Unit interval 399.88 VRX-DIFFp-p Differential input peak-to-peak voltage TRX-EYE Minimum receiver eye width NOM 400 0.175 MAX UNIT COMMENTS 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for SSC dictated variations (1) 1.200 V VRX-DIFFp-p = 2*|VRXP VRXN, | (2) 0.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 11.5 www.ti.com PCIe Differential Reference Clock Input Ranges (1) REFCLK+ and REFCLK– PARAMETER MIN NOM MAX UNIT COMMENTS fIN-DIFF Differential input frequency 100 MHz The input frequency is 100 MHz + 300 ppm and 2800 ppm including SSC-dictated variations. fIN-SE Single-ended input frequency 125 MHz The input frequency is 125 MHz + 300 ppm and 300 ppm. VRX-DIFFp-p Differential input peak-to-peak voltage VIH-SE 0.175 1.
XIO2213B www.ti.com 11.7 SCPS210F – OCTOBER 2008 – REVISED MAY 2013 Electrical Characteristics Over Recommended Operating Conditions (PHY Port Driver) PARAMETER TEST CONDITIONS 1394a differential output voltage VOD 56 Figure 11-1 MIN TYP 172 1394b differential output voltage MAX 265 700 UNIT mV IDIFF Driver difference current (TPA+, TPA–, TPB+, TPB–) Drivers enabled, speed signaling off 1.05 (1) 1.
XIO2213B SCPS210F – OCTOBER 2008 – REVISED MAY 2013 11.9 www.ti.com Electrical Characteristics Over Recommended Operating Conditions PHY Port Receiver PARAMETER ZID TEST CONDITIONS Differential impedance MIN TYP 4 7 Drivers disabled MAX UNIT k 4 pF 24 pF 20 k ZIC Common-mode impedance Drivers disabled VTH-R Receiver input threshold voltage Drivers disabled 30 30 mV VTH-CB Cable bias detect threshold. TPBx cable inputs Drivers disabled 0.
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