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XIO3130

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SLLS693F

May 2007–Revised January 2010

Summary of content (142 pages)

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XIO3130 XIO3130 Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Contents 1 2 3 4 2 Features ........................................................................................................................... 11 Introduction ...................................................................................................................... 12 ................................................................................................................. 12 ....................................
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 .................................................................................... ......................................................................................... Memory Limit Register ......................................................................................... Pre-fetchable Memory Base Register ........................................................................ Pre-Fetchable Memory Limit Register .................
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3 4 www.ti.com ...................................................................................... ...................................................................................... 4.2.64 GPIO D Control Register ...................................................................................... 4.2.65 GPIO Data Register ............................................................................................ 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 ................................................................. 96 ................................................................. 96 I/O Base Upper 16 Bits Register ............................................................................. 97 I/O Limit Upper 16 Bits Register .............................................................................. 97 Capabilities Pointer Register ....................................................
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 5 6 6 www.ti.com ......................................................................... 122 ...................................................................... 123 4.3.69 Correctable Error Status Register ........................................................................... 124 4.3.70 Correctable Error Mask Register ............................................................................ 125 4.3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 List of Figures 3-1 Block Diagram .................................................................................................................... 22 3-2 Power-Up Sequence Diagram .................................................................................................. 23 3-3 Power-Down Sequence Diagram 3-4 3-5 3-6 3-7 3-8 3-9 4-1 5-1 5-2 5-3 5-4 5-5 5-6 .......................................................................
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com List of Tables 2-1 XIO3130 Terminal Assignments................................................................................................ 14 2-2 XIO3130 Terminals Sorted Alphanumerically 2-3 XIO3130 Signal Names Sorted Alphabetically ...............................................................................
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XIO3130 www.ti.com 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 4-53 4-54 4-55 4-56 4-57 4-58 4-59 4-60 4-61 4-62 4-63 4-64 4-65 4-66 4-67 4-68 4-69 4-70 4-71 4-72 4-73 4-74 4-75 4-76 4-77 4-78 SLLS693F – MAY 2007 – REVISED JANUARY 2010 ...................................................................... Bit Descriptions – Serial Bus Control and Status Register .................................................................
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 4-79 4-80 4-81 4-82 4-83 4-84 4-85 4-86 4-87 4-88 4-89 4-90 5-1 5-2 5-3 10 www.ti.com ..................................................................................... Bit Descriptions – Slot Capabilities Register ............................................................................... Bit Descriptions – Slot Control Register .....................................................................................
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 XIO3130 Check for Samples: XIO3130 1 Features 12 • PCI Express Base Specification, Revision 1.1 • PCI Express Card Electromechanical Specification, Revision 1.1 • PCI-to-PCI Bridge Architecture Specification, Revision 1.1 • PCI Bus Power Management Interface Specification, Revision 1.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 2 www.ti.com Introduction The Texas Instruments XIO3130 switch is an integrated PCI Express fanout switch solution with one upstream x1 port and three downstream x1 ports. This high-performance integrated solution provides the latest in PCI Express switch technology including cut-through architecture, integrated reference clock buffers for downstream ports, integrated main power/VAUX power switch, and downstream port PCI Hot Plug® support.
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XIO3130 www.ti.com 2.3 SLLS693F – MAY 2007 – REVISED JANUARY 2010 Document Conventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 2.5 www.ti.com Terminal Assignments The XIO3130 is packaged in a 196-ball ZHC MicroStar™ BGA. Table 2-1.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 2-2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 2-3.
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XIO3130 www.ti.com 2.6 SLLS693F – MAY 2007 – REVISED JANUARY 2010 Terminal Descriptions Table 2-4. Power Supply Terminals Signal Ball I/O Type VDDA15(0) G04, H02, H04, J04, K03 PWR Filter 1.5-V analog power terminals for PCI-Express upstream port 0 VDDA15(1) A07, D07, D08, D09 PWR Filter 1.5-V analog power terminals for PCI-Express downstream port 1 VDDA15(2) G11, G12, H11, J11, J12 PWR Filter 1.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 2-6.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 2-8.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 2-10. GPIO Terminals Signal Ball I/O Type External Parts Description GPIO0 C06 LV CMOS I/O GPIO 0. If the DN1_DPSTRP pin is pulled high at the de-assertion of reset, this pin functions as the PRSNT hotplug pin for downstream port 1. Otherwise this pin’s function is programmed with the GPIO A Control register. GPIO1 B11 LV CMOS I/O GPIO 1.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 2-11. Miscellaneous Terminals Signal Ball I/O Type C02 LV CMOS IN GRST SDA SCL External Parts See description Description Global power-on reset input. Note: a pullup to Vaux (if supported) or VDD3.3 (if not) is required unless this terminal is always driven by the upstream device. D13 LV CMOS I/O Serial Data. This pin is the serial data pin for the EEPROM interface. B14 LV CMOS O Serial Clock.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 3 www.ti.com Description Figure 3-1 is the block diagram of the XIO3130. Clock Distribution/ Reset Logic PCI Express X1 Phy GPIO Port 0 (Up) Logic PCI Hot Plug Virtual PCI to PCI Bridge EEPROM Virtual PCI to PCI Bridge Bridge Virtual PCI to PCI Bridge Bridge Virtual PCI to PCI Bridge Bridge Port 1 (Down) Logic Port 2 (Down) Logic Port 3 (down) logic PCI Express x1 Phy PCI Express x1 Phy PCI Express x1 Phy Figure 3-1. Block Diagram 3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Figure 3-2. Power-Up Sequence Diagram 3.1.2 Power-Down Sequence • • • Assert PERST to the device. Remove the reference clock. Remove 3.3-V and 1.5-V voltages. See the power-down sequence diagram in Figure 3-3. If the VAUX33REF terminal is to remain powered after a system shutdown, the switch power-down sequence is exactly the same as shown in Figure 3-3. Figure 3-3. Power-Down Sequence Diagram 3.2 3.2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 3.2.3 www.ti.com Beacon The XIO3130 supports the PCI Express in-band beacon feature. Beacon is driven on the PCI Express link by the XIO3130 to request the re-application of main power when in the L2 link state. Once beacon is activated, the XIO3130 continues to send the beacon signal until main power is restored as indicated by PERST going inactive. At this time, the beacon signal is deactivated. 3.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 3-2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com edge of PERST or GRST, whichever occurs last, the SCL terminal is checked for a pullup resistor. If one is detected, bit 3 (SBDETECT) in the serial bus control and status register (see Table 4-32) is set. Software may disable the serial bus interface at any time by writing a zero to the SBDETECT bit. If no external EEPROM is required, the serial bus interface is permanently disabled by attaching a pulldown resistor to the SCL signal.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Figure 3-5. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. During a data transfer operation, an unlimited number of bytes are transmitted. However, each byte must be followed by an acknowledge bit to continue the data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com recognizes the slave address. Next, the XIO3130 sends the EEPROM word address, and another slave acknowledgment is expected. Then, the XIO3130 issues a restart condition followed by the 7-bit slave address and the R/W command bit equal to one (read). Once again, the slave device responds with acknowledge. Next, the slave device sends the 8-bit data byte, MS bit first.
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XIO3130 www.ti.com • • • SLLS693F – MAY 2007 – REVISED JANUARY 2010 EEPROM bytes 28h through 35h correspond to and are loaded into the configuration space for the first downstream virtual bridge or port 1 (see Figure 4-1). EEPROM bytes 36h through 43h correspond to and are loaded into the configuration space for the second downstream virtual bridge or port 2 (see Figure 4-1).
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 3-3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 This download table must be explicitly followed for the XIO3130 to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM. The XIO3130 addresses the serial EEPROM using a default slave address of 1010_000X binary. For an EEPROM download operation that occurs immediately after PERST, this address is fixed.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 3-5. Switch Reset Options Reset Option XIO3130 Feature Reset Response Internally-generated power-on reset During a power-on cycle, the XIO3130 asserts an internal reset and monitors the VDDCOMB15 (C01) terminal. When this terminal reaches 90% of the nominal input voltage specification, power is considered stable.
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XIO3130 www.ti.com 4 SLLS693F – MAY 2007 – REVISED JANUARY 2010 XIO3130 Configuration Register Space This chapter specifies the configuration registers that are used to enumerate the XIO3130 device within a PC system. An overview of the configuration register space is provided along with a detailed description of the register bits associated with the upstream and downstream ports of the XIO3130. 4.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.
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XIO3130 www.ti.com 4.2.1 SLLS693F – MAY 2007 – REVISED JANUARY 2010 PCI Configuration Space (Upstream Port) Register Map Table 4-1.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-2. Extended Configuration Space (Upstream Port) Register Name Next Capability Offset / Capability Version 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-3. Bit Descriptions – Command Register BIT FIELD NAME ACCESS 15:11 RSVD r 10 INT_DISABLE rw 9 FBB_ENB r DESCRIPTION Reserved. When read, these bits return zeros. INTx disable. This bit is used to enable device-specific interrupts. The XIO3130 upstream port does not generate any interrupts internally, so this bit is ignored. The XIO3130 does forward INTx messages from downstream ports to the upstream port.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-4. Bit Descriptions – Status Register BIT 15 FIELD NAME PAR_ERR ACCESS rcu DESCRIPTION Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP on the upstream port. This bit is set regardless of the state of the Parity Error Response bit in the Command Register. 0 – No parity error detected. 1 – Parity Error detected. Signaled system error.
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XIO3130 www.ti.com 4.2.6 SLLS693F – MAY 2007 – REVISED JANUARY 2010 Class Code and Revision ID Register This read-only register categorizes the Base Class, Sub Class, and Programming Interface of the XIO3130. The Base Class is 06h, identifying the device as bridge device. The Sub Class is 04h, identifying the function as a PCI-to-PCI bridge, and the Programming Interface is 00h. Also, the TI chip revision is indicated in the lower byte (02h).
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.9 www.ti.com Header Type Register This read-only register indicates that this function has a type one PCI header. Bit seven of this register is a zero, indicating that the upstream port is a single device. PCI register offset: 0Eh Register type: Read Only Default value: 01h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.13 Subordinate Bus Number This register specifies the bus number of the highest number PCI bus segment that is downstream of the XIO3130’s upstream port. The XIO3130 uses this register to determine how to respond to a Type 1 configuration transaction. PCI register offset: 1Ah Register type: Read/Write Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.16 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the XIO3130 forwards downstream. PCI register offset: 1Dh Register type: Read/Write; Read Only Default value: 01h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Table 4-7. Bit Descriptions – I/O Limit Register BIT FIELD NAME ACCESS DESCRIPTION I/O limit.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the XIO3130 forwards downstream. PCI register offset: 20h Register type: Read/Write; Read Only Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-9.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-11. Bit Descriptions – Pre-fetchable Memory Base Register BIT FIELD NAME ACCESS DESCRIPTION 15:4 PREBASE rw Pre-fetchable memory base. This field defines the bottom address of the pre-fetchable memory address range that is used to determine when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 0.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.23 Pre-fetchable Limit Upper 32 Bits Register This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Limit register.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.26 Capabilities Pointer Register This read-only register provides a pointer into the PCI configuration header where the PCI power management block resides. Since the PCI power management registers begin at 50h, this register is hardwired to 50h. PCI register offset: 34h Register type: Read only Default value: 50h BIT NUMBER RESET STATE 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 0 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-17. Bit Descriptions – Bridge Control Register BIT FIELD NAME ACCESS 15:12 RSVD r Reserved. When read, these bits return zeros. 11 DTSERR r Discard timer SERR enable. This bit is hardwired to zero. This bit does not apply to PCI Express. 10 DTSTATUS r Discard timer status. This bit is hardwired to zero. This bit does not apply to PCI Express. 9 SEC_DT r Secondary discard timer. This bit is hardwired to zero.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-17. Bit Descriptions – Bridge Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 0 PERR_EN rw Parity error response enable. It is assumed that the relevant error checking is unnecessary for the XIO3130’s internal PCI bus; therefore, setting this bit has no effect. 4.2.30 Capability ID Register This read-only register identifies the linked list item as the register for PCI power management.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-18. Bit Descriptions – Power Management Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 8:6 AUX_CURRENT r 3.3-VAUX auxiliary current requirements. This field is hardwired to 3’b000. See PCI Power Management Specification Revision 1.2, Section 3.2.3, Page 26, for mapping this field to specific current consumption values. 5 DSI r Device-specific initialization.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.34 Power Management Bridge Support Extension Register This read-only register is used to indicate to host software the state of the secondary bus when the XIO3130 is placed in D3. PCI register offset: 56h Register type: Read only Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-20.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.2.38 MSI Message Control Register This register is used to control the sending of MSI messages. PCI register offset: 72h Register type: Read/Write; Read Only Default value: 0080h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-21.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-22. Bit Descriptions – MSI Message Address Register BIT FIELD NAME ACCESS 31:2 ADDRESS rw 1:0 RSVD r DESCRIPTION System Specified Message Address. Reserved. When read, these bits return zeros. 4.2.40 MSI Message Upper Address Register This register contains the upper 32 bits of the address that a MSI message shall be written to when an interrupt is to be signaled.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 1 4.2.43 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the XIO3130. This register reads 90h, which points to the PCI Express Capabilities registers. PCI register offset: 81h Register type: Read only Default value: 90h BIT NUMBER RESET STATE 7 1 6 0 5 0 4 1 3 0 2 0 1 0 0 0 4.2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.47 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the XIO3130. This register reads 00h, which indicates that no additional capabilities are supported. PCI register offset: 91h Register type: Read only Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-25. Bit Descriptions – Device Capabilities Register BIT FIELD NAME ACCESS 31:28 RSVD r DESCRIPTION Reserved. When read, these bits return zeros. Captured slot power limit scale. The value in this register is programmed by the host by issuing a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received, bits 9:8 are written to this field.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-26. Bit Descriptions – Device Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 11 ENS r Enable no snoop. Since the XIO3130 does not initiate such transactions, this bit is read-only zero. 10 APPE r Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal amount of AUX power when PME is disabled. 9 PFE r Phantom function enable.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-27. Bit Descriptions – Device Status Register BIT FIELD NAME ACCESS 15:6 RSVD r Reserved. When read, these bits return zeros. DESCRIPTION 5 PEND ru Transaction PENDING. This bit is set when the XIO3130 has issued a non-posted transaction that has not been completed yet. AUX power detected. This bit indicates that AUX power is present.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-28. Bit Descriptions – Link Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 9:4 MLW r Maximum link width. This field is encoded 000001b to indicate that the device only supports an x1 PCI Express link. 3:0 MLS r Maximum link speed. This field is encoded 0001b to indicate that the device supports a maximum link speed of 2.5 Gb/s. 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.54 Link Status Register The Link Status register indicates the current state of the PCI Express Link. PCI register offset: A2h Register type: Read only Default value: 1X11h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 1 11 0 10 x 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 1 Table 4-30. Bit Descriptions – Link Status Register BIT FIELD NAME ACCESS 15:13 RSVD r Reserved. When read, these bits return zeros.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.57 Serial Bus Slave Address Register The Serial Bus Slave Address register is used to indicate the address of the device being targeted by the serial bus cycle. This register also indicates whether the cycle will be a read or a write cycle. Writing to this register initiates the cycle on the serial interface. This register is reset with PERST. The default value corresponds to a serial EEPROM slave address of 7’b101_0000.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-32. Bit Descriptions – Serial Bus Control and Status Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the XIO3130 device is downloading register defaults from a serial EEPROM. 4 ROMBUSY 0 – No EEPROM activity ru 1 – EEPROM download in progress This field is reset with PERST. Serial EEPROM detected.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register BIT FIELD NAME ACCESS 15:14 RSVD r DESCRIPTION Reserved. When read, these bits return zeros. Endpoint L0s acceptable latency. This field is used to program the maximum acceptable latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field in the Device Capabilities register.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register (continued) BIT FIELD NAME ACCESS DESCRIPTION L1 exit latency. This field is used to program the maximum latency for the PHY to exit the L1 state. This field is used to set the L1 Exit Latency field in the Link Capabilities register.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-34. Bit Descriptions – Global Chip Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Minimum power scale. This value is programmed to indicate the scale of the Minimum Power Value field. 00 – 1.0x 21:20 MIN_POWER_SCA LE 01 – 0.1x rw 10 – 0.01x 11 – 0.001x This field is loaded from EEPROM (when present) and reset with PERST. 19:12 MIN_POWER_VAL UE Minimum power value.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-35. Bit Descriptions – GPIO A Control Register BIT FIELD NAME ACCESS 15 RSVD r DESCRIPTION Reserved. Reads back zero. GPIO 4 Control.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-35. Bit Descriptions – GPIO A Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 1 Control.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-36. Bit Descriptions – GPIO B Control Register BIT FIELD NAME ACCESS 15 RSVD r DESCRIPTION Reserved, reads back zero GPIO 9 Control.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-36. Bit Descriptions – GPIO B Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 6 Control.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-37. Bit Descriptions – GPIO C Control Register BIT FIELD NAME ACCESS 15 RSVD r DESCRIPTION Reserved. Reads back zero. GPIO 14 Control.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-37. Bit Descriptions – GPIO C Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 10 Control.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-38. Bit Descriptions – GPIO D Control Register BIT FIELD NAME ACCESS 15:10 RSVD r DESCRIPTION Reserved. When read, these bits return zeros. GPIO 18 Control.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.65 GPIO Data Register This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in output mode. Reads to this register return the state of the GPIO pins, regardless of PCI Hot Plug strapping or GPIO configuration. Writes to this register only affect pins that are configured as a general purpose output.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-39. Bit Descriptions – GPIO Data Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 14 data. 14 PCIE_GPIO14_DATA rw GP Input mode: reads state of pin; writes have no affect GP Output mode: reads and also controls state of pin This field is loaded from EEPROM (if present), and reset with FRST. GPIO 13 data.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-39. Bit Descriptions – GPIO Data Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 6 data. GP Input mode: reads state of pin; writes have no affect GP Output mode: reads and also controls state of pin 6 PCIE_GPIO6_DATA rw Program-selectable HP input pin This field is valid only if DN2_DPSTRP == 0. If this bit field is valid then it is loaded from EEPROM (if present), and reset with FRST.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.66 TI Proprietary Register This read/write TI proprietary register is located at offset C8h and controls TI proprietary functions. This register must not be changed from the specified default state. If the default value is changed in error, a PCI Express Reset (PERST) returns this register to a default state. If an EEPROM is used to load configuration registers, the value loaded for this register must be 00000001h.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.69 TI Proprietary Register This read/write TI proprietary register is located at offset D4h and controls TI proprietary functions. This register must not be changed from the specified default state. If the default value is changed in error, a PCI Express Reset (PERST) returns this register to a default state. If an EEPROM is used to load configuration registers, the value loaded for register D5h must be 10h.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.72 Subsystem Access Register This register is a read/write register. The contents of this register are aliased to the Subsystem Vendor ID and Subsystem ID registers at PCI Offsets 84h and 86h for all PCI Express ports.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.74 Downstream Ports Link PM Latency Register This read/write register is used to program L0s and L1 exit latencies for all XIO3130 downstream ports. Similar information is provided in a separate register for the upstream port. PCI register offset: E8h Register type: Read/Write; Read Only Default value: 3F24h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-42.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register (continued) BIT FIELD NAME ACCESS DESCRIPTION L1 exit latency. This field is used to program the maximum latency for the PHY to exit the L1 state. This is used to set the L1 Exit Latency field in the Link Capabilities register.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-43. Bit Descriptions – Global Switch Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Beacon detect disable. This bit disables beacon detection on all downstream ports and allows the reference macro to be placed in low power state during D3cold. 0 BCN_DET_DIS 0 – Beacon detection enabled rwh 1 – Beacon detection disabled This field is loaded from EEPROM (when present) and reset with GRST. 4.2.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-44. Uncorrectable Error Status Register BIT FIELD NAME ACCESS 31:21 RSVD r DESCRIPTION 20 UR_ERROR rcuh Unsupported Request error. This bit is asserted when an Unsupported Request error is detected (i.e., when a request is received that results in the sending of a completion with an Unsupported Request status). 19 ECRC_ERROR rcuh Extended CRC error. This bit is asserted when an Extended CRC error is detected.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-45. Uncorrectable Error Mask Register (continued) BIT FIELD NAME ACCESS 18 MAL_TLP_MASK rwh DESCRIPTION Malformed TLP mask. 0 - Error condition is unmasked. 1 - Error condition is masked. Receiver Overflow mask. 17 RX_OVERFLOW_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked. Unexpected Completion mask. 16 UNXP_CPL_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-46. Uncorrectable Error Severity Register BIT FIELD NAME ACCESS 31:21 RSVD r DESCRIPTION Reserved. Return zeros when read. Unsupported Request error severity. 20 UR_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL. 1 - Error condition is signaled using ERR_FATAL. Extended CRC error severity. 19 ECRC_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-47. Correctable Error Status Register BIT FIELD NAME ACCESS 31:14 RSVD r DESCRIPTION 13 ANFES rcuh Advisory nonfatal error status. 12 REPLAY_TMOUT rcuh Replay timer timeout.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-48. Correctable Error Mask Register (continued) BIT FIELD NAME ACCESS 8 REPLAY_ROLL_MASK rwh DESCRIPTION REPLAY_NUM rollover mask. 0 – Error condition is unmasked 1 – Error condition is masked Bad DLLP error mask. 7 BAD_DLLP_MASK rwh 0 – Error condition is unmasked 1 – Error condition is masked Bad TLP error mask.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.84 Header Log Register The Header Log register stores the TLP header for the packet that lead to the most recently detected error condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW TLP header).
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XIO3130 www.ti.com 4.3 SLLS693F – MAY 2007 – REVISED JANUARY 2010 PCI Express Downstream Port Registers The default reset domain for all downstream port registers is SBRST. Some register fields are placed in a different reset domain from the default reset domain; all bit and field descriptions identify any unique reset domains. Generally, all sticky bits are placed in the GRST domain and all (non-sticky) EEPROM loadable bits are placed in the PERST domain. 4.3.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-51. Extended Configuration Space (Downstream Port) Register Name Next Capability Offset / Capability Version 4.3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-52. Bit Descriptions – Command Register BIT FIELD NAME ACCESS 15:11 RSVD r DESCRIPTION Reserved. When read, these bits return zeros. INTx disable. This bit is used to enable device-specific INTx interrupts. The XIO3130 downstream ports can generate INTx interrupts due to PCI Hot Plug events. The XIO3130 forwards INTx messages from downstream ports to the upstream port (see INTx Support section) regardless of this bit.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-53. Bit Descriptions – Status Register (continued) BIT FIELD NAME ACCESS 13 MABORT r Received master abort. This bit is hardwired to zero. It is assumed that the relevant error checking is unnecessary for the XIO3130 internal PCI bus. 12 TABORT_REC r Received target abort. This bit is hardwired to zero. It is assumed that the relevant error checking is unnecessary for the XIO3130 internal PCI bus.
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XIO3130 www.ti.com 4.3.7 SLLS693F – MAY 2007 – REVISED JANUARY 2010 Cache Line Size Register The Cache Line Size register is implemented by PCI Express devices as a read-write field for legacy compatibility, but has no impact on any PCI Express device functionality. PCI register offset: 0Ch Register type: Read/Write Default value: 00h BIT NUMBER RESET STATE 4.3.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.11 Primary Bus Number This register specifies the bus number of the PCI bus segment for the downstream port primary interface (i.e., the internal PCI bus). PCI register offset: 18h Register type: Read/Write Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.3.12 Secondary Bus Number This register specifies the bus number of the PCI bus segment for the downstream port secondary interface (i.e.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.15 I/O Base Register This read/write register specifies the lower limit of the I/O addresses that the XIO3130 downstream port forwards downstream. PCI register offset: 1Ch Register type: Read/Write; Read Only Default value: 01h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Table 4-55. Bit Descriptions – I/O Base Register BIT FIELD NAME ACCESS DESCRIPTION I/O base.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-57. Bit Descriptions – Secondary Status Register BIT 15 FIELD NAME ACCESS PAR_ERR DESCRIPTION Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP on the downstream port. This bit is set regardless of the state of the Parity Error Response bit in the Bridge Control register. rcu 0 – No parity error detected. 1 – Parity error detected. Received System Error.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.19 Memory Limit Register This read/write register specifies the upper limit of the memory addresses that the downstream port forwards downstream. PCI register offset: 22h Register type: Read/Write; Read Only Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-59.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-61. Bit Descriptions – Pre-fetchable Memory Limit Register BIT FIELD NAME ACCESS DESCRIPTION 15:4 PRELIMIT rw Pre-fetchable memory limit. This field defines the top address of the pre-fetchable memory address range that is used to determine when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.24 I/O Base Upper 16 Bits Register This read/write register specifies the upper 16 bits of the I/O Base register. PCI register offset: 30h Register type: Read/Write Default value: 0000h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-64. Bit Descriptions – I/O Base Upper 16 Bits Register BIT 15:0 FIELD NAME ACCESS IOBASE DESCRIPTION I/O base upper 16 bits.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.27 Interrupt Line Register This read/write register, which the system programs, indicates to the software which interrupt line that the XIO3130 downstream port has assigned to it. The default value of this register is FFh, which indicates that an interrupt line has not yet been assigned to the function. This register is essentially a scratch-pad register; it has no effect on the XIO3130 itself.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-66. Bit Descriptions – Bridge Control Register (continued) BIT 6 FIELD NAME SRST ACCESS rw DESCRIPTION Secondary bus reset. This bit is set when the software resets all devices downstream of the XIO3130 downstream port. Setting this bit causes the downstream port to send a reset downstream via a training sequence. 0 – Downstream port not in Reset state 1 – Downstream port in Reset state 5 MAM r Master abort mode.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.30 Capability ID Register This read-only register identifies the linked list item as the register for PCI power management. It returns 01h when read. PCI register offset: 50h Register type: Read only Default value: 01h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 4.3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-67. Bit Descriptions – Power Management Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 5 DSI r Device-specific initialization. This bit returns 0 when read, which indicates that the XIO3130 does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD r Reserved. When read, this bit returns zero. 3 PME_CLK r PME clock.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.34 Power Management Bridge Support Extension Register This read-only register is used to indicate to the host software what the state of the downstream port’s secondary bus will be when the downstream port is placed in D3. PCI register offset: 56h Register type: Read only Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-69.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.3.38 MSI Message Control Register This register is used to control the sending of MSI messages. PCI register offset: 72h Register type: Read/Write; Read Only Default value: 0080h BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-70.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-71. Bit Descriptions – MSI Message Address Register BIT FIELD NAME ACCESS 31:2 ADDRESS rw 1:0 RSVD r DESCRIPTION System-specified message address. Reserved. When read, these bits return zeros. 4.3.40 MSI Message Upper Address Register This read/write register contains the upper 32 bits of the address that a MSI message shall be written to when an interrupt is to be signaled.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.43 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the XIO3130 downstream port. This register reads 90h, which points to the PCI Express Capabilities registers. PCI register offset: 81h Register type: Read only Default value: 90h BIT NUMBER RESET STATE 7 1 6 0 5 0 4 1 3 0 2 0 1 0 0 0 4.3.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.47 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the XIO3130 downstream port. This register reads 00h, which indicates that no additional capabilities are supported. PCI register offset: 91h Register type: Read only Default value: 00h BIT NUMBER RESET STATE 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.3.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-74. Bit Descriptions – Device Capabilities Register BIT FIELD NAME ACCESS 31:28 RSVD r Reserved. When read, these bits return zeros. DESCRIPTION 27:26 CSPLS ru Captured slot power limit scale. This field is only applicable to upstream ports and is hardwired to zero. 25:18 CSPLV ru Captured slot power limit value. This field is only applicable to upstream ports and is hardwired to zero. 17:16 RSVD r Reserved.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-75. Bit Descriptions – Device Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 10 APPE r Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal amount of AUX power when PME is disabled. 9 PFE r Phantom function enable. Since the XIO3130 part does not support phantom functions, this bit is read-only zero. 8 ETFE r Extended tag field enable.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-76. Bit Descriptions – Device Status Register BIT FIELD NAME ACCESS 15:6 RSVD r Reserved. When read, these bits return zeros. 5 PEND ru Transaction pending. This bit is set when the XIO3130 downstream port has issued a non-posted transaction that has not been completed yet. 4 APD DESCRIPTION AUX power detected. This bit indicates that AUX power is present.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-77. Bit Descriptions – Link Capabilities Register (continued) BIT 17:15 FIELD NAME ACCESS L1_LATENCY DESCRIPTION r L1 exit latency. This field indicates the time required to transition from the L1 state to the L0 state. This field is a direct reflection of the Downstream Ports Link PM Latency register L1_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present).
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-78. Bit Descriptions – Link Control Register (continued) BIT 3 FIELD NAME ACCESS DESCRIPTION r Read completion boundary. This bit specifies the minimum size read completion packet that the XIO3130 can send when breaking a read request into multiple completion packets. This field is not applicable to XIO3130; i.e., the XIO3130 does not break up completion packets and is hardwired to zero.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 1 5 1 4 0 3 0 2 0 1 0 0 0 Table 4-80. Bit Descriptions – Slot Capabilities Register BIT 31:19 18 FIELD NAME SLOT_NUM EMILP ACCESS r ru DESCRIPTION Physical slot number. This field indicates a system-dependent physical slot number that is unique to each slot in the system. This field can be programmed by writing to the General Slot Info register.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-80. Bit Descriptions – Slot Capabilities Register (continued) BIT 2 FIELD NAME ACCESS MRLSP DESCRIPTION Manual retention latch sensor present. This bit indicates whether a manual retention latch (MRL) sensor is implemented on the chassis for this slot. This bit can be programmed by writing to the General Control register bit 10, which is SLOT_MRLSP. For more information on the General Control register, see section 3.3.61.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-81. Bit Descriptions – Slot Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Power indicator control. When read, this field indicates the current state of the power indicator. Writes set the power indicator state. When writes cause this field to change, the appropriate POWER_INDICATOR_* messages are sent. This bit controls the PWR_LED output pin.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-81. Bit Descriptions – Slot Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Attention button pressed enable. This bit enables generation of a •＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt •＝＝＝＝＝＝＝＝＝ PME when the ABP bit in the Slot Status register is asserted. 0 ABP_EN rw 0 – Disabled 1 – Enabled HPI_EN and MSI_EN (see Table 3ἱ21) must also be enabled for interrupt generation.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-82. Bit Descriptions – Slot Status Register (continued) BIT FIELD NAME ACCESS 2 MRLSC ruc DESCRIPTION MRL sensor changed. This bit indicates whether the state of the MRLSS bit has changed. 0 – MRLSS bit has not changed. 1 – MRLSS bit has changed. Power fault detected. This bit indicates the state of the PWRFLT pin. 1 PFD ruc 0 – PWRFLT pin de-asserted (no power fault at slot). 1 – PWRFLT pin asserted (power fault at slot).
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.60 TI Proprietary Register This read/write TI proprietary register is located at offset D0h and controls TI proprietary functions. This register must not be changed from the specified default state. If the default value is changed in error, a PCI Express Reset (PERST) returns this register to a default state. If an EEPROM is used to load configuration registers, the value loaded for this register must be 3214 0000h.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-83. Bit Descriptions – General Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION PCI Hot Plug surprise. This bit indicates whether a device present in this slot can be removed from the system without prior notification. This bit is used to control the PCI Hot Plug surprise (HPS) field in the Slot Capabilities register.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-83. Bit Descriptions – General Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Electromechanical interlock present. This bit indicates whether an electromechanical interlock is implemented on the chassis for this slot. This bit is used to control the EMILP field in the Slot Capabilities register.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-84. Bit Descriptions – General Slot Info Register BIT FIELD NAME ACCESS DESCRIPTION Slot number. This field is used to program the Physical Slot Number field in the Slot Capabilities register. This field is loaded from EEPROM (if present) and reset with PERST. 15:3 SLOT_NUM rw 2:0 RSVD r Reserved.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-85. Uncorrectable Error Status Register BIT FIELD NAME ACCESS 31:21 RSVD r DESCRIPTION 20 UR_ERROR rcuh Unsupported Request error. This bit is asserted when an Unsupported Request error is detected (i.e., when a request is received that results in the sending of a completion with an Unsupported Request status). 19 ECRC_ERROR rcuh Extended CRC error. This bit is asserted when an Extended CRC error is detected.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-86. Uncorrectable Error Mask Register (continued) BIT FIELD NAME ACCESS 18 MAL_TLP_MASK rwh DESCRIPTION Malformed TLP mask. 0 - Error condition is unmasked. 1 - Error condition is masked. Receiver Overflow mask. 17 RX_OVERFLOW_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked. Unexpected Completion mask. 16 UNXP_CPL_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-87. Uncorrectable Error Severity Register BIT FIELD NAME ACCESS 31:21 RSVD r DESCRIPTION Reserved. Return zeros when read. Unsupported Request error severity. 20 UR_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL. 1 - Error condition is signaled using ERR_FATAL. Extended CRC error severity. 19 ECRC_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER RESET STATE 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 BIT NUMBER RESET STATE 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Table 4-88. Correctable Error Status Register BIT FIELD NAME ACCESS 31:14 RSVD r 13 ANFES rcuh Advisory nonfatal error status. 12 REPLAY_TMOUT rcuh Replay timer timeout.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-89. Correctable Error Mask Register (continued) BIT FIELD NAME ACCESS 7 BAD_DLLP_MASK rwh DESCRIPTION Bad DLLP error mask. 0 – Error condition is unmasked 1 – Error condition is masked Bad TLP error mask. 6 BAD_TLP_MASK rwh 0 – Error condition is unmasked 1 – Error condition is masked 5:1 RSVD r Reserved. Return zeros when read. 0 RX_ERROR_MASK rwh Receiver error mask.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 5 PCI Hot Plug Implementation Overview 5.1 PCI Hot Plug Architecture Overview The PCI Express architecture is designed to natively support both hot-add and hot-removal (collectively Hot-Plug) of adapters. The architecture also provides a ‘toolbox’ of mechanisms that allow different user/operator models to be supported using a self-consistent infrastructure.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 5-1. GPIO Matrix (continued) GPIO[#] 0 EMILENG3 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 In Table 2-11, S indicates a strapping option. If the appropriate DNn_DPSTRP pin is pulled high, the GPIO is mapped to this value and is no longer mapped by the GPIO Control register. Each downstream port of the XIO3130 is assigned one dedicated sideband pin, DNn_PERST.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 5.2 www.ti.com PCI Hot Plug Timing 5.2.1 Power-Up Cycle The XIO3130 switch can be powered up numerous ways depending on the way the DPSTRP[2:0] strapping defines the port. The different power-up cycles are: nonPCI Hot Plug power-up cycle, PCI Hot Plug power-up cycle with PWRGDn feedback, and PCI Hot Plug power-up cycle without PWRGDn feedback. 5.2.1.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 power-up cycle. The XIO3130 switch asserts PWRONn and because the PWRGDn signal is tied high, the power-up cycle starts as soon as PWRONn is asserted. After 100 ms, REFCLKn is enabled, and a 100 ms time-out starts. After the 100 ms time-out completes, PERSTn is de-asserted. If the port has been programmed (see GPIO Control registers in sections Section 4.2.61 through Section 4.2.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com PRSNTn# PWRONn# CLKREQn# Stable REFCLKn PERSTn# PWRGDn <500 ns <100 ms Figure 5-5. Surprise Removal In the case of surprise removal, the XIO3130 switch de-asserts PERST within 500 ns after a de-bounced PRSNTn de-asserted state exists. Then REFCLKn is disabled, and the PWRONn signal is de-asserted within 100 ms. 5.2.2.3 PWRGDn De-Assertion Another situation that forces a PCI Hot Plug port to power-down is the de-assertion of PWRGDn.
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XIO3130 www.ti.com 5.2.4 SLLS693F – MAY 2007 – REVISED JANUARY 2010 Debounce Circuits Integrated de-bounce circuits are provided for the following input pins: • PRSNT[2:0] present detects for each downstream port; used with PCI Express or ExpressCard (formerly NEWCARD) slots. • ATN_BTN[2:0], which are attention button inputs, are MUXed onto GPIO pins; de-bounce is only needed when the relevant GPIO pins are programmed to this mode.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 6 www.ti.com Electrical Characteristics This chapter describes the electrical characteristics of the XIO3130. Absolute Maximum Ratings (1) 6.1 over operating free-air temperature range (unless otherwise noted) VDDRC, VAUX33REF, VDD33REF VDDAREF, VDDA, VDDD, VDD15 Input voltage range VO Output voltage range Tstg (1) (2) (3) UNIT –0.5 to 3.6 V –0.5 to 1.65 V Supply voltage range PCI Express (PER) VI VALUE –0.6 to 0.
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XIO3130 www.ti.com 6.3 SLLS693F – MAY 2007 – REVISED JANUARY 2010 PCI Express Differential Transmitter Output Ranges PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS UI Unit interval PETP, PETN 399.88 400 400.12 ps Each UI is 400 ps ±300 ppm. UI does not account for SSC dictated variations.See (1) VTX-DIFFp-p Differential peak-to-peak output voltage PETP, PETN 0.8 1.2 V VTX-DIFFp-p = 2*|VTXP – VTXN|.
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com PCI Express Differential Transmitter Output Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS UI Maximum time to meet all TX specifications when transitioning from electrical idle to sending differential data. This value is considered a de-bounce time for the TX to meet all TX specifications after leaving electrical idle. 10 dB Measured over 50 MHz to 1.25 GHz. See (5) PETP, PETN 6 dB Measured over 50 MHz to 1.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 PCI Express Differential Receiver Input Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS RLRX-DIFF Differential return loss PERP, PERN 10 dB Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and –300 mV, respectively. See (4) RLRX-CM Common mode return loss PERP, PERN 6 dB Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and –300 mV, respectively. See (4).
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XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 6.6 www.ti.com PCI Express Reference Clock Output Requirements SYMBOL 100-MHz INPUT PARAMETER MIN MAX UNIT NOTES Rise Edge Rate Rising edge rate 0.6 4 V/ns See (1) and (2) Fall Edge Rate Falling edge rate 0.
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XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 3.3-V I/O Electrical Characteristics (1) 6.7 PARAMETER OPERATIONS (2) VIH High-level input voltage VIL Low-level input voltage (2) VI Input voltage TEST CONDITIONS 0.7 VDD33 VDD33 V 0 0.3 VDD33 V 0 VDD33 V 0 VDD33 V 0 25 ns 0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.