TMS320C6201 Digital Signal Processor Silicon Errata SPRZ153 November 2000 Copyright 2000, Texas Instruments Incorporated
TMS320C6201 Silicon Errata SPRZ153 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Quality and Reliability Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C6201 Silicon Errata SPRZ153 Advisory 2.1.19 PMEMC: Branch from External to Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero Transfer Count . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 7 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . Advisory 2.0.
TMS320C6201 Silicon Errata 1 SPRZ153 Introduction This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon releases 3.1, 3.0, 2.1, and 2.0. 1.1 Quality and Reliability Conditions TMX Definition Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability for products classified as “TMX.
TMS320C6201 Silicon Errata 1.2 SPRZ153 Revision Identification The device revision can be determined by the lot trace code marked on the top of the package. The location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are listed in Table 1. Figure 1. Example, Lot Trace Code for TMS320C6201 DSP DSP TMS320C6201GJL TMS320C6201GJL Cxx–YMLLLLS C31–YMLLLLS Lot trace code Lot trace code with revision 3.
TMS320C6201 Silicon Errata 2 SPRZ153 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles C6201B NO NO. 4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid UNIT MIN MAX –4 6 ns 6 ns –4 ns Table 3. JTAG Test-Port Timing C6201, C6201B NO.
TMS320C6201 Silicon Errata SPRZ153 Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) SSCLK 1 2 CE 3 BE_ [3:0] 4 BE1 BE2 BE3 BE4 EA [21:2] A1 A2 A3 A4 ED [31:0] Q1 5 6 13 Q2 14 Q3 Q4 9 10 15 16 SSADS SSOE SSWE NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since these timings are specified as minimums.
TMS320C6201 Silicon Errata 3 SPRZ153 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Advisory 3.1.1 Issues When Pausing at a Block Boundary Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: The following problems exist when a DMA channel is paused at a block boundary: Workaround: Advisory 3.1.2 • DMA does not flush internal FIFO when a channel is paused across block boundary. As a result, data from old and new blocks of that channel are in FIFO simultaneously.
TMS320C6201 Silicon Errata Advisory 3.1.3 SPRZ153 DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: If a DMA channel is configured to do a multiframe split-mode transfer with SRC_DIR = Index (11b), the source address is always modified using the Element Index, even during the last element transfer of a frame.
TMS320C6201 Silicon Errata SPRZ153 Advisory 3.1.6 DMA Paused During Emulation Halt Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: When running an autoinitialized transfer, the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register. The read state machine functions properly in this case. The problem exists only at block boundaries.
TMS320C6201 Silicon Errata SPRZ153 Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3 memory map (0x03FFFC00). Advisory 3.1.9 Cache During Emulation With Extremely Slow External Memory Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: If a program requests fetch packet “A” followed immediately by fetch packet “B”, and all of the following four conditions are true: 1. A and B are separated by a multiple of 64K in memory (i.e.
TMS320C6201 Silicon Errata 4 SPRZ153 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications Advisory 3.0.8 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Revision(s) Affected: 3.0, 2.1, and 2.0 Details: A speedpath in the device causes SDCLK and SSCLK to start up 180 degrees out-of-phase (effectively inverted) from the desired waveform.
TMS320C6201 Silicon Errata SPRZ153 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) 2. On SBSRAM/SDRAM reads, data will be sampled on the falling edge before the rising edge that would be expected. In this case, the input setup time for data at the C62xt is reduced by 1 CPU cycle. Note that this case can be compounded with Case 1. The control signals could be latched one SSCLK/SDCLK cycle (2 CPU cycles) late by the memories.
TMS320C6201 Silicon Errata SPRZ153 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) Alternate Workaround: Resolution The following alternate workarounds can help for certain board and layout configurations. • Using faster (125 MHz or PC100) SDRAMs and/or SBSRAMs will reduce the chances of data corruption and/or increase the frequency at which reliable memory operation can be observed.
TMS320C6201 Silicon Errata 5 SPRZ153 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications Advisory 2.1.1 EMIF: CE Space Crossing on Continuous Request Not Allowed Revision(s) Affected: 2.1 and 2.0 Details: Any continuous request of the EMIF cannot cross CE address space boundaries. This condition can result in bad data read, or writing to the wrong CE.
TMS320C6201 Silicon Errata SPRZ153 EMIF: SDRAM Invalid Access (Continued) Workaround: Avoid use of multiple CE spaces of SDRAM within a single refresh period. Advisory 2.1.4 Revision(s) Affected: DMA: RSYNC Cleared Late for Frame-synchronized Transfer 2.1 and 2.0 In a frame-synchronized transfer, RSYNC is only cleared after the beginning of last write transfer. It should occur after the start of the first read transfer in the synchronized frame.
TMS320C6201 Silicon Errata SPRZ153 McBSP: DXR to XSR Copy Not Generated (Continued) Example: Configure the DMA as follows: (a) For half-word/byte-size accesses with right justification on receive data: – ch_A: /* for transmit */ src_address = mem_out; dst_address = DXR; Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 2 /* change this to 1 for byte writes */ – ch_B : /* for receive */ src_address = DRR; dst_address = mem_in; Element_size = HALF /* change this to BYTE for 8-b element size */
TMS320C6201 Silicon Errata SPRZ153 McBSP: DXR to XSR Copy Not Generated (Continued) (c) For byte-size writes with right justification on receive data: – ch_A: /* for transmit */ dst_address = DXR+3; /* 0x018C0007 for McBSP0 or 0x01900007 for McBSP1 */ Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 1 – ch_B : /* for receive */ src_address = DRR+3 /* 0x018C0003 for McBSP0 or 0x01900003 for McBSP1 */ dst_address = mem_in; Element_size = BYTE; Address_inc_mode = = inc_by_ element_size /* inc_
TMS320C6201 Silicon Errata SPRZ153 Advisory 2.1.7 DMA Channel 0 Multiframe Split-Mode Incompletion Revision(s) Affected: 2.1 and 2.0 Details: If DMA Channel 0 is configured to perform a multiframe split-mode transfer, it is possible for the last element of the last frame of the Receive Read to not be transferred.
TMS320C6201 Silicon Errata SPRZ153 McBSP: Incorrect mLaw Companding Value Advisory 2.1.11 Revision(s) Affected: 2.1 and 2.0 Details: The C6201 McBSP m-Law/A-Law companding hardware produces an incorrectly expanded m-Law value. McBSP receives m-Law value 0111 1111, representing a mid-scale analog value. Expanded 16-bit data is 1000 0000 0000 0000, representing a most negative value. Expected value is 0000 0000 0000 0000. McBSP expands µ-Law 1111 1111 (also mid-scale value) correctly.
TMS320C6201 Silicon Errata Advisory 2.1.14 SPRZ153 EMIF: HOLD Request Causes Problems With SDRAM Refresh Revision(s) Affected: 2.1 and 2.0 Details: If the HOLD interface is used in a system with SDRAM, there are some situations that are likely to occur. If the NOHOLD bit is not set and an external requester attempts to gain control of the bus via the HOLD signal of the EMIF at the exact same time when the EMIF is issuing a SDRAM Refresh command, the HOLD request is never recognized.
TMS320C6201 Silicon Errata Advisory 2.1.16 SPRZ153 DMA Split-mode Receive Transfer Incomplete After Pause Revision(s) Affected: 2.1 and 2.0 Details: If the DMA is performing a split-mode transfer and the channel is paused after all Transmit Reads in a frame are completed but before the Receive Reads are completed, then the Receive Transfer will not complete after the channel is restarted.
TMS320C6201 Silicon Errata Advisory 2.1.19 SPRZ153 PMEMC: Branch from External to Internal Revision(s) Affected: 2.1 and 2.0 Details: The program flow is corrupted after branching from external memory to internal program memory when the following are true: • CPU is executing from external memory • A CPU stall occurs that holds the CPU until all pending program fetches complete.
TMS320C6201 Silicon Errata 6 SPRZ153 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Advisory 2.0.1 Program Fetch: Cache Modes Not Functional Revision(s) Affected: 2.0 Workaround: Use internal program memory in mapped mode. Advisory 2.0.2 Bootload: Boot from 16-Bit and 32-Bit Asynchronous ROMs Not Functional Revision(s) Affected: 2.0 Details: 16-bit-wide ROM mode and 32-bit-wide asynchronous mode work in run time without bugs. The problem is only in boot.
TMS320C6201 Silicon Errata Advisory 2.0.5 SPRZ153 Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location Sequenced Wrong Revision(s) Affected: 2.
TMS320C6201 Silicon Errata SPRZ153 Advisory 2.0.9 McBSP New Block Interrupt Does Not Occur for Start of Block 0 Revision(s) Affected: 2.0 Details: When end-of-block interrupt is selected ((R/X)INTM=01b), McBSP new block interrupt does not occur at end of frame (i.e., before block 0). (Internal reference number 4357) Workaround: This interrupt is used when on-the-fly channel selection/enabling is being performed. A static channel selection/enabling avoids this. Advisory 2.0.
TMS320C6201 Silicon Errata SPRZ153 Advisory 2.0.13 McBSP: XEMPTY Stays Low When DXR Written Late Revision(s) Affected: 2.0 Details: XEMPTY goes low and stays low when DXR was written on either the last bit or next-to-last bit of the previous word being transferred to DX. (Internal Reference Number 3383) Advisory 2.0.14 EMIF: Multiple SDRAM CE Spaces: Invalid Access After Refresh Revision(s) Affected: 2.0 Details: This bug exists only in those systems that have SDRAMs in more than one CE space.
TMS320C6201 Silicon Errata SPRZ153 Advisory 2.0.19 EMIF: Data Setup Times Revision(s) Affected: 2.0 Details: The data setup time for the external memory interface is listed in the February 21, 1998 Advanced Information TMSX320C6201 Data Sheet as 2 ns, 3 ns, and 2 ns for full-rate SBSRAM, half-rate SBSRAM, and SDRAM, respectively. In revision 2.0 of silicon, these values are to 4.8, 6.0, and 6.
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