User's Manual

SPRZ153

TMS320C6201 Silicon Errata

EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued)

2. On SBSRAM/SDRAM reads, data will be sampled on the falling edge before the rising edge

that would be expected. In this case, the input setup time for data at the C62xt is reduced by

1 CPU cycle. Note that this case can be compounded with Case 1. The control signals could

be latched one SSCLK/SDCLK cycle (2 CPU cycles) late by the memories. Thus, the setup

could be reduced by up to 3 CPU cycles and be more than an entire SSCLK/SDCLK late.

Figure 6. Read Example – Desired Behavior

tacc

tisu

CLKOUT1 (CPU Clock)

SS/SDCLK Internal

SS/SDCLK External

Read Data

Figure 7. Read Example – Failing Behavior

tacc

tisu

CLKOUT1 (CPU Clock)

SS/SDCLK Internal

SS/SDCLK External

Read Data

CLKOUT2 is also affected by this speedpath bug and is 180 degrees out-of-phase. It behaves

in the same way as SDCLK. (Internal reference number C601307)

Workaround:

• For prototypes, raising the core supply to 1.9 – 2.1 V corrects this problem. This is not

recommended in boards shipped to customers, since the manufacturing process is

not designed to be reliable outside the normal operating range. This option allows the

user to verify current board designs at all valid frequency ranges.

• Reduce the operating frequency of the TMS320C6201B until SSCLK/SDCLK has the

desired relationship. Typically, this occurs at 175 MHz across the range of recommended

operating conditions.

• Since SSCLK and SDCLK are inverted externally relative to each other by design,

these signals can be swapped on external memory interfaces to correct the problem

(SSCLK to SDRAM and SDCLK to SBSRAM). This will cause invalid operation at

frequencies below 175 MHz and will not work with future silicon revisions.

• If CLKOUT2 is used as an SDRAM clock, follow all the workarounds for SDCLK.

C62x is a trademark of Texas Instruments Incorporated.