User's Manual

SPRZ153

TMS320C6201 Silicon Errata

Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note)

BE1

BE2

BE3

BE4

A1 A2 A3 A4

Q3 Q4

1615

109

1413

SSCLK

BE_ [3:0]

EA [21:2]

ED [31:0]

SSADS

SSOE

SSWE

NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since

these timings are specified as minimums. However, the CE

output setup and hold time may be greater than that shown

in the data sheet in multiples of P ns. In other words, for output setup time, the CEx

transition from high to low may happen P,

2P, …, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CEx

low-to-high transition may

happen P, 2P, …, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1

and 2 in Figure 2, and Figure 3.