! " ### $% &' " %( ) ") * + Data Manual June 2004 Connectivity Solutions SCPS081
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Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1.1 PCI7621 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1.2 PCI7421 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 1.1.3 PCI7611 Controller . . . . . . . . . . . . . . . .
Section 3.6 3.7 3.8 3.9 iv Title 3.5.8 SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3.5.9 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3.5.10 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11 48-MHz Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Serial-Bus Interface Implementation . . . . .
Section 4 Title PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Register Map (Functions 0 and 1) . . . . . . . . . . . . . 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Device ID Register Functions 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.
Section 4.42 4.43 4.44 4.45 5 6 vi Title Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.
Section 7 8 Title OHCI Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section Title 8.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . .
Section Title Page 10.4 Vendor-Dependent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−6 10.5 Power-Class Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−7 11 Flash Media Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . 11−1 11.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−2 11.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . .
Section Title Page 12.16 Slot Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−10 12.17 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . 12−11 12.18 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . 12−12 12.19 Power Management Control and Status Register . . . . . . . . . . . . . . 12−13 12.20 Power Management Bridge Support Extension Register . . . . . . . . 12−13 12.
Section Title Page 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14−1 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges . 14−1 14.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 14−1 14.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14−4 14.
List of Illustrations Figure 2−1 2−2 2−3 2−4 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 3−18 3−19 3−20 3−21 5−1 5−2 6−1 14−1 xii Title PCI7621 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . PCI7421 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . PCI7611 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . PCI7411 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 2−17 2−18 2−19 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 Title Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Names by GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . .
Table 3−18 3−19 4−1 4−2 4−3 4−4 4−5 4−6 4−7 4−8 4−9 4−10 4−11 4−12 4−13 4−14 4−15 4−16 4−17 4−18 4−19 4−20 4−21 4−22 4−23 4−24 4−25 5−1 5−2 5−3 5−4 5−5 5−6 5−7 5−8 5−9 5−10 5−11 5−12 xiv Title Function 4 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Function 5 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table Title 5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14 ExCA Card Detect and General Control Register Description . . . . . . . . . 5−15 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6−1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8−11 8−12 8−13 8−14 8−15 8−16 8−17 8−18 8−19 8−20 8−21 8−22 8−23 8−24 8−25 8−26 8−27 8−28 8−29 8−30 8−31 8−32 8−33 8−34 8−35 9−1 9−2 9−3 9−4 10−1 10−2 10−3 10−4 10−5 10−6 10−7 10−8 10−9 11−1 11−2 11−3 11−4 xvi Title Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . .
Table 11−5 11−6 11−7 11−8 11−9 11−10 11−11 11−12 11−13 11−14 11−15 11−16 12−1 12−2 12−3 12−4 12−5 12−6 12−7 12−8 12−9 12−10 12−11 12−12 12−13 12−14 12−15 12−16 12−17 13−1 13−2 13−3 13−4 13−5 13−6 13−7 13−8 13−9 13−10 13−11 13−12 13−13 13−14 Title Page Latency Timer and Class Cache Line Size Register Description . . . . . . . 11−5 Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . 11−6 Flash Media Base Address Register Description . . . . . . . . . . . . . . . . . . .
Table Title Page 13−15 Smart Card Configuration 1 Register Description . . . . . . . . . . . . . . . . . . . 13−16 13−16 Smart Card Configuration 2 Register Description . . . . . . . . . . . . . . . . . . .
1 Introduction The Texas Instruments PCI7621 controller is an integrated dual-socket UltraMedia PC Card controller, Smart Card controller, IEEE 1394 open HCI host controller and PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart Card, IEEE 1394, Secure Digital (SD), MultiMediaCard (MMC), Memory Stick/PRO, SmartMedia, and XD technology.
Function 5 of the PCI7621 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards. 1.1.2 PCI7421 Controller The PCI7421 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance. Function 4 of the PCI7611 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket.
1.2 Features The PCI7x21/PCI7x11 controller supports the following features: 1−4 • PC Card Standard 8.1 compliant • PCI Bus Power Management Interface Specification 1.1 compliant • Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant • PCI Local Bus Specification Revision 2.3 compliant • PC 98/99 and PC2001 compliant • Windows Logo Program 2.
• External cycle timer control for customized synchronization • Extended resume signaling for compatibility with legacy DV components • PHY-Link logic performs system initialization and arbitration functions • PHY-Link encode and decode functions included for data-strobe bit level encoding • PHY-Link incoming data resynchronized to local clock • Low-cost 24.
• SD Memory Card Specifications, SD Group, March 2000 • Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro) • ISO Standards for Identification Cards ISO/IEC 7816 • SD Host Controller Standard Specification, rev. 1.0 • Memory Stick Format Specification, Sony Confidential, ver. 2.0 • SmartMedia Standard 2000, May 19, 2000 1.4 Trademarks Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc.
1.5 Terms and Definitions Terms and definitions used in this document are given in Table 1−1. Table 1−1. Terms and Definitions TERM DEFINITIONS AT AT (advanced technology, as in PC AT) attachment interface ATA driver An existing host software component that loads when any flash media adapter and card is inserted into a PC Card socket. This driver is logically attached to a predefined CIS provided by the PCI7x21/PCI7x11 controller when the adapter and media are both inserted.
1−8
2 Terminal Descriptions The PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI7621 package. Figure 2−2 is a pin diagram of the PCI7421 package. Figure 2−3 is a pin diagram of the PCI7611 package. Figure 2−4 is a pin diagram of the PCI7411 package.
W AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 AD4 AD0 TPB0N TPA0N TPB1N NC TPA1N TPA0P TPB1P AVDD TPA1P VDPLL _33 R0 R1 V AD30 AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11 AD7 AD3 PC2 TPB0P (TEST3) U REQ AD31 AD28 AD25 AD22 AD17 IRDY SERR AD14 AD10 AD6 AD2 PC1 AGND TPBIAS0 AGND TPBIAS1 (TEST2) T GRST GNT RI_OUT //PME R MFUNC6 SUSPEND PRST P MFUNC2 MFUNC3 MFUNC4 VSSPLL VDPLL _15 AD21 PCLK PAR B_CAD7 //B_D7 B_CAD9 B_CC/BE0 //B_A10 //
W AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 AD4 AD0 TPB0N TPA0N TPB1N NC TPA1N TPA0P TPB1P AVDD TPA1P VDPLL _33 R0 R1 VSSPLL VDPLL _15 RSVD PHY_ TEST_ MA XI XO CNA RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD V AD30 AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11
W AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 AD4 AD0 TPB0N TPA0N TPB1N NC TPA1N TPA0P TPB1P AVDD TPA1P VDPLL_ 33 R0 R1 VSSPLL VDPLL_ 15 RSVD PHY_ TEST_ MA XI XO CNA RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD V AD30 AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11
Table 2−1.
Table 2−1.
Table 2−1.
Table 2−1.
Table 2−2.
Table 2−2.
Table 2−3.
Table 2−3.
2.1 Detailed Terminal Descriptions Please see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines the column headings and the abbreviations used in the detailed terminal description tables.
Table 2−4. Power Supply Terminals Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals. TERMINAL NAME DESCRIPTION NUMBER I/O TYPE INPUT EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) N12, U14, U16 Analog circuit ground terminals GND AVDD R13, R14, V17 Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 µF and 0.001 µF.
Table 2−5. PC Card Power Switch Terminals Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT EXTERNAL COMPONENTS TTLI1 TTLO1 PCMCIA power switch CLOCK L06 Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK.
Table 2−7. PCI Address and Data Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals. TERMINAL NAME NO.
Table 2−8. PCI Interface Control Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals. TERMINAL DESCRIPTION I/O TYPE N08 PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the controller terminates the cycle with an initiator abort.
Table 2−9. Multifunction and Miscellaneous Terminals The power rail designation is not applicable for the multifunction and miscellaneous terminals. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) A_USB_EN B_USB_EN E02 E01 USB enable. These output terminals control an external CBT switch for each socket when an USB card is inserted into the socket. O CLK_48 M01 A 48-MHz clock must be connected to this terminal.
Table 2−10. 16-Bit PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card address and data terminal is unused, then the terminal may be left floating. SOCKET A TERMINAL SOCKET B TERMINAL† NAME NO.
Table 2−11. 16-Bit PC Card Interface Control Terminals External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL NAME A_BVD1 (STSCHG/RI) NO. B02 SKT B TERMINAL† NAME B_BVD1 (STSCHG/RI) DESCRIPTION NO. F14 Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries.
Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued) SKT A TERMINAL NAME A_OE A_READY (IREQ) NO. C12 C04 SKT B TERMINAL† NAME B_OE B_READY (IREQ) DESCRIPTION I/O TYPE Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The controller asserts OE to indicate TC for a DMA write operation.
Table 2−12. CardBus PC Card Interface System Terminals A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating. SKT A TERMINAL NAME A_CCLK A_CCLKRUN A_CRST NO. E09 C03 A06 SKT B TERMINAL† NAME B_CCLK B_CCLKRUN B_CRST NO. DESCRIPTION INPUT OUTPUT PU/ PD POWER RAIL H18 CardBus clock.
Table 2−13. CardBus PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL† NAME NO. NAME NO.
Table 2−14. CardBus PC Card Interface Control Terminals If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL† INPUT OUTPUT PU/ PD I PCII4 PCIO4 PU3 VCCA/ VCCB I/O PCII4 PCIO4 PU3 VCCA/ VCCB CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
Table 2−14. CardBus PC Card Interface Control Terminals (Continued) SKT A TERMINAL NAME NO. SKT B TERMINAL† NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL PCIO4 PU3 VCCA/ VCCB SW1 VCCA/ VCCB A_CSTOP A09 B_CSTOP J17 CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers.
Table 2−15. IEEE 1394 Physical Layer Terminals TERMINAL DESCRIPTION I/O TYPE P15 Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. If it is not used, then this terminal must be strapped either to DVDD or GND through a resistor. The CNA terminal can be disabled by setting bit 7 (CNAOUT) of the PCI PHY control register at offset ECh in the PCI configuration space (see Section 7.22, PCI PHY Control Register). This bit is loaded by the serial EEPROM.
Table 2−16. SD/MMC Terminals If any SD/MMC terminal is unused, then the terminal may be left floating. TERMINAL DESCRIPTION I/O TYPE Media card power control for flash media sockets. O E03 SD/MMC card detect. This input is asserted when SD/MMC cards are inserted. I SD_CLK J05, G05 SD flash clock. This output provides the SD/MMC clock, which operates at 16 MHz. I/O SD_CMD J03, F03 SD flash command. This signal provides the SD command per the SD Memory Card Specifications.
Table 2−18. Smart Media/XD Terminals If any Smart Media/XD terminal is unused, then the terminal may be left floating. TERMINAL NAME NO. DESCRIPTION I/O TYPE Media card power control for flash media sockets. O LVCO1 TTLO2 MC_PWR_CTRL_0 F01 MC_PWR_CTRL_1 F02 SM_ALE J03 SmartMedia address latch enable. This signal functions as specified in the SmartMedia specification, and is used to latch addresses passed over SM_D7−SM_D0. O SM_CD F06 SmartMedia card detect.
Table 2−19. Smart Card Terminals † If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be connected to 5 V. TERMINAL NAME NO. DESCRIPTION I/O TYPE INPUT TTLI2 OUTPUT PU/ PD POWER RAIL SW2 VCC SC_CD L02 Smart Card card detect. This input is asserted when Smart Cards are inserted. I SC_CLK K05 Smart Card clock. The controller drives a 3-MHz clock to the Smart Card interface when enabled.
2−30
3 Feature/Protocol Descriptions The following sections give an overview of the PCI7x21/PCI7x11 controller. Figure 3−1 shows the connections to the PCI7x21/PCI7x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
3.2 I/O Characteristics The PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs. VCCP Tied for Open Drain OE Pad Figure 3−2. 3-State Bidirectional Buffer 3.
3.4.2 Device Resets The following are the requirements for proper reset of the PCI7x21/PCI7x11 controller: 1. GRST and PRST must both be asserted at power on. 2. GRST must be asserted for at least 2 ms at power on 3. PRST must be deasserted either at the same time or after GRST is asserted 4. PCLK must be stable for 100 µs before PRST is deasserted. > 2 ms > 0 ns VCC GRST PRST PCLK > 100 ms Figure 3−3. PCI Reset Requirement 3.4.
as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI offset B3h, see Section 4.50) causes the PCI7x21/PCI7x11 controller to route the SDA and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections 4.47, 4.48, and 4.
3.4.5 Function 2 (OHCI 1394) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25, Subsystem Access Register). See Table 7−22 for a complete description of the register contents.
3.5.1 PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the card-detect and voltage-sense signals.
Table 3−2. PC Card—Card Detect and Voltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface Ground Ground Ground Ground Ground 16-bit PC Card VCC 5V VPP/VCORE Per CIS (VPP) Open Open 5V Open Ground 5V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP) Ground Ground Ground 5V 16-bit PC Card 5 V, 3.3 V, and Per CIS (VPP) Ground Ground Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP) Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.
3.5.5 Power Switch Interface The power switch interface of the PCI7x21/PCI7x11 controller is a 3-pin serial interface. This 3-pin interface is implemented such that the PCI7x21/PCI7x11 controller can connect to both the TPS2226 and TPS2228 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.31) selects the power switch that is implemented. The PCI7x21/PCI7x11 controller defaults to use the control logic for the TPS2228 power switch.
3.5.7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card configurations. The PCI7x21/PCI7x11 controller has integrated all of these pullup resistors and requires no additional external components.
Current Limiting R ≈ 150 Ω MFUNCx PCI7x21/ PCI7x11 MFUNCy Current Limiting R ≈ 150 Ω Socket A LED Socket B LED Figure 3−6. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
• Frequency stability (overtemperature and age): A crystal with ±30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm.
SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal.
Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI7x21/PCI7x11 master.
Table 3−9.
Table 3−9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 25h PCI 2Ch, subsystem vendor ID, byte 0 26h PCI 2Dh, subsystem vendor ID, byte 1 27h PCI 2Eh, subsystem ID, byte 0 28h PCI 2Fh, subsystem ID, byte 1 29h PCI F4h, Link_Enh, byte 0, bits 7, 2, 1 OHCI 50h, host controller control, bit 23 2Ah [7] [6] [5:3] [2] [1] [0] Link_Enh. enab_unfair HCControl.Program Phy Enable RSVD Link_Enh, bit 2 Link_Enh.
Table 3−9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 49h PCI 94h, slot 0 3.3 V maximum current 4Ah PCI 98h, slot 1 3.3 V maximum current 4Bh PCI 9Ch, slot 2 3.3 V maximum current 4Ch Reserved (PCI A0h, slot 3 3.3 V maximum current) 4Dh Reserved (PCI A4h, slot 4 3.3 V maximum current) 4Eh Reserved (PCI A8h, slot 5 3.
3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.
Table 3−11. PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card battery conditions.
Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to the flag-cleared-on-read method.
The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.24). Table 3−12 summarizes the interrupt signaling modes. Table 3−12. Interrupt Pin Register Cross Reference INTRTIE Bit TIEALL Bit INTPIN Function 0 (CardBus) 0 0 0x01 (INTA) 0x02 (INTB) 0x03 (INTC) 1 0 0x01 (INTA) 0x01 (INTA) 0x03 (INTC) X 1 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 3.7.
• • • • Ring indicate PCI power management Cardbus bridge power management ACPI support PCI Bus EEPROM SD/MMC MS/MSPRO SM/xD PCI7x21/P CI7x11 SD/MMC 1394a Socket Power Switch Power Switch Power Switch PC Card/ UltraMedia Card PC Card/ UltraMedia Card † The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI7x21/PCI7x11 controller. PRST must be asserted for subsequent warm resets. Figure 3−13.
3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) The PCI7x21/PCI7x11 controller requires 1.5-V core voltage. The core power can be supplied by the PCI7x21/PCI7x11 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal. Table 3−14 lists the requirements for both the internal core power supply and the external core power supply. Table 3−14. Requirements for Internal/External 1.
3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does not.
places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI7x21/PCI7x11 controller when SUSPEND is asserted because the outputs are in a high-impedance state. The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the appropriate PCI7x21/PCI7x11 registers. 3.8.
3.8.9 PCI Power Management 3.8.9.1 CardBus Power Management (Functions 0 and 1) The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. 3.8.9.2 OHCI 1394 (Function 2) Power Management The PCI7x21/PCI7x11 controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power management definition in the 1394 Open Host Controller Interface Specification, Appendix A4. Table 3−16.
The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-up issues in the following manner: • • Two resets are provided to handle preservation of PME context bits: − Global reset (GRST) is used only on the initial boot up of the system after power up. It places the PCI7x21/PCI7x11 controller in its default state and requires BIOS to configure the controller before becoming fully functional. − PCI reset (PRST) has dual functionality based on whether PME is enabled or not.
• • • • • • ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0 ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6 Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0 Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0 Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1 Socket control register (CardBus offset 10h, see Section 6.
The global reset-only (function 3) register bits: • • • • • Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0 Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0 Power management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0 General control register (PCI offset 4Ch, see Section 11.21): bits 6−4, 2–0 Diagnostic register (PCI offset 54h, see Section 11.
3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection PCI7x21/ PCI7x11 400 kΩ CPS Cable Power Pair 1 µF TPBIAS 56 Ω 56 Ω TPA+ Cable Pair A TPA− Cable Port TPB+ Cable Pair B TPB− 56 Ω 220 pF (see Note A) 56 Ω 5 kΩ Outer Shield Termination NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. Figure 3−17. TP Cable Connections Outer Cable Shield 1 MΩ 0.01 µF 0.001 µF Chassis Ground Figure 3−18.
Outer Cable Shield Chassis Ground Figure 3−19. Non-DC Isolated Outer Shield Termination 3.9.2 Crystal Selection The PCI7x21/PCI7x11 controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.
C9 X1 X1 24.576 MHz IS CPHY + CBD X0 C10 Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout.
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1: • Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus.
3−34
4 PC Card Controller Programming Model This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by § in Table 4−2.
Table 4−2.
4.3 Device ID Register Functions 0 and 1 This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller functions (PCI functions 0 and 1).
4.4 Command Register The PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register are shared among the PCI7x21/PCI7x11 PCI functions. Three command registers exist in the PCI7x21/PCI7x11 controller, one for each function.
Table 4−3. Command Register Description (continued) BIT SIGNAL TYPE FUNCTION 1 MEM_EN RW Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI memory space. 0 = Disables the PCI7x21/PCI7x11 response to memory space accesses (default) 1 = Enables the PCI7x21/PCI7x11 response to memory space accesses RW I/O space control. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI I/O space.
Table 4−4. Status Register Description (continued) BIT SIGNAL TYPE FUNCTION 4 CAPLIST R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (PCI offset 04h, see Section 4.
4.9 Latency Timer Register The latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles. When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the transaction when its GNT is deasserted.
4.12 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only, returning 0s when read.
4.14 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on a per-socket basis. See Table 4−5 for a complete description of the register contents.
4.15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.
4.18 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI7x21/PCI7x11 CardBus interface, in units of CCLK cycles. When the PCI7x21/PCI7x11 controller is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the transaction at the end of the next data phase.
4.20 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the PCI7x21/PCI7x11 controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s.
4.22 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the PCI7x21/PCI7x11 controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space.
4.24 Interrupt Pin Register The value read from this register is function dependent. The default value for function 0 is 01h (INTA), the default value for function 1 is 02h (INTB), the default value for function 2 is 03h (INTC), the default value for function 3 is 01h (INTA), the default value for function 4 is 01h (INTA), the default value for function 5 is 01h (INTA).
Register: Offset: Type: Default: (function 5) Interrupt pin 3Dh Read-only 01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4), 04h Table 4−6.
Table 4−7. Bridge Control Register Description (Continued) BIT SIGNAL 6† CRST TYPE RW FUNCTION CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted. 1 = CRST is asserted (default). This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST. Master abort mode.
4.27 Subsystem ID Register The subsystem ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
4.29 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4−8 for a complete description of the register contents.
Table 4−8. System Control Register Description (continued) BIT SIGNAL TYPE FUNCTION 22 ‡ CBRSVD RW CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low when a CardBus card has been inserted. When this bit is low, these signals are placed in a high-impedance state. 0 = Place the CardBus RSVD terminals in a high-impedance state. 1 = Drive the CardBus RSVD terminals low (default). 21 ‡ VCCPROT RW VCC protection enable. This bit is socket dependent.
Table 4−8. System Control Register Description (continued) BIT SIGNAL TYPE 4 ‡§ CB_DPAR RW 3 ‡§ RSVD R Reserved. This bit returns 0 when read. 2‡ EXCAPOWER R ExCA power control bit. 0 = Enables 3.3 V (default) 1 = Enables 5 V 1 ‡§ KEEPCLK RW FUNCTION CardBus data parity SERR signaling enable. 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal Keep clock.
4.31 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete description of the register contents.
Table 4−9. General Control Register Description BIT SIGNAL 15 ‡ FM_PWR_CTRL _POL TYPE FUNCTION RW Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 and MC_PWR_CTRL_1 terminals. 0 = MC_PWR_CTRL_x terminals are active low (default) 1 = MC_PWR_CTRL_x terminals are active high Smart Card interface select. This bit controls the selection of the dedicated Smart Card interface used by the controller.
4.32 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can be programmed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete description of the register contents.
4.33 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 General-purpose event enable RW RW R RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: General-purpose event enable 89h Read-only, Read/Write 00h Table 4−11.
4.35 General-Purpose Output Register The general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 General-purpose output Type R R R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: General-purpose output 8Bh Read-only, Read/Write 00h Table 4−13.
4.36 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial EEPROM. See Table 4−14 for a complete description of the register contents.
Table 4−14. Multifunction Routing Status Register Description (Continued) BIT 7−4 ‡ 3−0 ‡ SIGNAL MFUNC1 MFUNC0 TYPE FUNCTION RW Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LEDA1 0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = LEDA2 0110 = RSVD 1010 = IRQ10 1110 = GPE 0010 = INTB 0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 0 configuration.
4.38 Card Control Register The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. See Table 4−16 for a complete description of the register contents. The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.
4.39 Device Control Register The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register. The socket-capable force bits are also programmed through this register. See Table 4−17 for a complete description of the register contents.
4.40 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written to it. See Table 4−18 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 RW R RW RW RW RW RW RW 0 1 1 0 0 0 0 0 Name Type Default Diagnostic Register: Offset: Type: Default: Diagnostic 93h (functions 0, 1) Read/Write 60h Table 4−18.
4.41 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. Bit 7 6 5 4 Name 3 2 1 0 Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Offset: Type: Default: Capability ID A0h Read-only 01h 4.
4.43 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management. Both PCI7x21/PCI7x11 CardBus bridge functions support D0, D1, D2, and D3 power states. Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification revision 1.1. See Table 4−19 for a complete description of the register contents.
4.44 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI7x21/PCI7x11 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 4−20 for a complete description of the register contents.
4.45 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−21 for a complete description of the register contents.
4.47 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
4.49 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit.
4.50 Serial Bus Control/Status Register The serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 4−25 for a complete description of the register contents.
4−38
5 ExCA Compatibility Registers (Functions 0 and 1) The ExCA (exchangeable card architecture) registers implemented in the PCI7x21/PCI7x11 controller are register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller.
Host I/O Space Offset PCI7x21/PCI7x11 Configuration Registers Offset 00h PC Card A ExCA Registers CardBus Socket/ExCA Base Address 10h Index 3Fh Data 16-Bit Legacy-Mode Base Address 40h 44h PC Card B ExCA Registers 7Fh Note: The 16-bit legacy-mode base address register is shared by function 0 and 1 as indicated by the shading. Offset of desired register is placed in the index register and the data from that location is returned in the data register. Figure 5−1.
Table 5−1.
Table 5−1.
5.1 ExCA Identification and Revision Register This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See Table 5−2 for a complete description of the register contents. NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only.
5.2 ExCA Interface Status Register This register provides information on current status of the PC Card interface. An X in the default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete description of the register contents.
5.3 ExCA Power Control Register This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete description of the register contents.
5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents.
5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active.
5.6 ExCA Card Status-Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See Table 5−8 for a complete description of the register contents.
5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI7x21/PCI7x11 controller does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 5−9 for a complete description of the register contents.
5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5−10 for a complete description of the register contents. Bit 7 6 5 RW RW RW RW 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW RW RW 0 0 0 0 ExCA I/O window control Register: Type: Offset: Default: ExCA I/O window control Read/Write CardBus socket address + 807h: Card A ExCA offset 07h Card B ExCA offset 47h 00h Table 5−10.
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the start address.
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 5−11 for a complete description of the register contents.
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the end address.
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete description of the register contents.
5.19 ExCA Card Detect and General Control Register This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the VS1 and VS2 signals at the PC Card interface. Table 5−14 describes each bit in the ExCA card detect and general control register.
5.20 ExCA Global Control Register This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in this register are retained for 82365SL-DF compatibility. See Table 5−15 for a complete description of the register contents.
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
5.23 ExCA Memory Windows 0−4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16-Mbyte regions in the 4-gigabyte PCI address space.
6 CardBus Socket Registers (Functions 0 and 1) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI7x21/PCI7x11 controller provides the CardBus socket/ExCA base address register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Each function has a separate base address register for accessing the CardBus socket registers (see Figure 6−1).
6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset.
6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents.
6.3 Socket Present State Register This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI7x21/PCI7x11 controller uses the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this register.
Table 6−4. Socket Present State Register Description (Continued) BIT SIGNAL TYPE 9† BADVCCREQ R 8† DATALOST R FUNCTION Bad VCC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software Data lost.
Table 6−5. Socket Force Event Register Description BIT SIGNAL TYPE 31−15 RSVD R Reserved. These bits return 0s when read. 14 CVSTEST W Card VS test. When this bit is set, the PCI7x21/PCI7x11 controller reinterrogates the PC Card, updates the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control. 13 FYVCARD W Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h, see Section 6.3) to be written.
6.5 Socket Control Register This register provides control of the voltages applied to the socket VPP and VCC. The PCI7x21/PCI7x11 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6 for a complete description of the register contents.
6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.
7.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h Read-only 104Ch 7.
7.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a complete description of the register contents.
7.4 Status Register The status register provides status over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−3 for a complete description of the register contents.
7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI7x21/PCI7x11 controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7−4 for a complete description of the register contents.
7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x11 PCI header type and no built-in self-test. See Table 7−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 1 0 0 0 0 0 0 0 Header type and BIST Register: Offset: Type: Default: Header type and BIST 0Eh Read-only 0080h Table 7−6.
7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7−8 for a complete description of the register contents.
7.10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. See Table 7−9 for a complete description of the register contents.
7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See Table 7−10 for a complete description of the register contents.
7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See Table 7−11 for a complete description of the register contents. Bit 7 6 5 4 Name 3 2 1 0 Interrupt line Type Default RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: Interrupt line 3Ch Read/Write FFh Table 7−11. Interrupt Line Register Description BIT FIELD NAME 7−0 INTR_LINE TYPE DESCRIPTION RW Interrupt line.
7.16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST.
7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 7−15 for a complete description of the register contents.
7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI7x21/PCI7x11 controller related to PCI power management. See Table 7−16 for a complete description of the register contents.
7.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power-management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 7−17 for a complete description of the register contents.
7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−19 for a complete description of the register contents.
7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−20 for a complete description of the register contents.
Table 7−20. PCI Miscellaneous Configuration Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1‡ DISABLE_ PCIGATE RW When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 0‡ KEEP_PCLK RW When bit 0 is set to 1, the PCI clock is always kept running through the CLKRUN protocol. When this bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6.
Table 7−21. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE 11 RSVD R DESCRIPTION 10 ‡ enab_mpeg_ts RW 9 RSVD R 8‡ enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0. 7‡ enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration.
7.26 GPIO Control Register The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can be configured as GPIO0 by setting bit 7 (DISABLE_BMC) to 1. The LPS terminal can be configured as GPIO1 by setting bit 15 (DISABLE_LPS) to 1. See Table 7−23 for a complete description of the register contents.
Table 7−23. GPIO Control Register Description (Continued) BIT 7−20 SIGNAL TYPE FUNCTION GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for GPIO1. 0 = High-impedance output (default) 1 = Output is enabled 12 GPIO_ENB1 R/W 11−9 RSVD R 8 GPIO_DATA1 R/W GPIO1 data. When bit 15 (DISABLE_LPS) is set to 1 and GPIO1 output is enabled, the value written to this bit represents the logical data driven to the GPIO1 terminal.
8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x11 IEEE 1394 link function. This section provides the register interface and bit descriptions.
Table 8−1.
Table 8−1.
8.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8−2 for a complete description of the register contents.
8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8−3 for a complete description of the register contents.
8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x11 controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8−4 for a complete description of the register contents.
8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource.
8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents.
8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete description of the register contents.
8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST.
8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 8−8 for a complete description of the register contents.
8.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 8−10 for a complete description of the register contents.
8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the PCI7x21/PCI7x11 controller. See Table 8−11 for a complete description of the register contents.
Table 8−11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit. 21−20 RSVD R 19 LPS RSC Reserved. Bits 21 and 20 return 0s when read. Bit 19 controls the link power status.
8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents.
8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 8−13 for a complete description of the register contents.
Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE 6 isoChannel38 RSC When bit 6 is set to 1, the controller is enabled to receive from isochronous channel number 38. DESCRIPTION 5 isoChannel37 RSC When bit 5 is set to 1, the controller is enabled to receive from isochronous channel number 37. 4 isoChannel36 RSC When bit 4 is set to 1, the controller is enabled to receive from isochronous channel number 36.
8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x11 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
Table 8−15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start.
8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCI7x21/PCI7x11 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 8−15.
Table 8−16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this register-access-failed interrupt mask enables interrupt generation. 17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see Section 8.
8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 8.
8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 8−17.
8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.
8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 8−18.
8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−20 for a complete description of the register contents.
8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the register contents.
8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the PCI7x21/PCI7x11 controller. It contains controls for the receiver and cycle timer. See Table 8−23 for a complete description of the register contents.
8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the register contents.
8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of the register contents.
8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the PCI7x21/PCI7x11 controller is cycle master, this register is transmitted with the cycle start message. When the PCI7x21/PCI7x11 controller is not cycle master, this register is loaded with the data field in an incoming cycle start.
8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, then the packet is not acknowledged and the request is not queued.
Table 8−27. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the controller from that node are accepted. 17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the controller from that node are accepted.
8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8−28 for a complete description of the register contents.
8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register.
Table 8−29. Physical Request Filter High Register Description (Continued) 8−36 BIT FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, physical requests received by the controller from that node are handled through the physical request context. 17 physReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, physical requests received by the controller from that node are handled through the physical request context.
8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register.
8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8−31 for a complete description of the register contents.
8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1. See Table 8−32 for a complete description of the register contents.
8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 8−33 for a complete description of the register contents.
8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1. The isochronous transmit DMA context command pointer can be read when a context is active.
Table 8−34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 29 cycleMatchEnable RSCU When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24−12) in the isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register.
8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8−35 for a complete description of the register contents.
9 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9−1 for the TI extension register listing. Table 9−1.
9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1).
Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE 7−6 RSVD R DESCRIPTION 5 DV_Branch1 RSC When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place.
9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 8.
Table 9−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 9 RSVD R 8‡ enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0. 7‡ enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
9−6
10 PHY Register Configuration There are 16 accessible internal registers in the PCI7x21/PCI7x11 controller. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. 10.
Table 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 R Root. This bit indicates that this node is the root node. The R bit is cleared to 0 by bus reset and is set to 1 during tree-ID if this node becomes root. CPS 1 R Cable-power-status.
Table 10−2. Base Register Field Descriptions (Continued) FIELD ISBR SIZE TYPE DESCRIPTION 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µs) arbitrated bus reset at the next opportunity. This bit is cleared to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets.
10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3 shows the configuration of the port status page registers and Table 10−4 shows the corresponding field descriptions. If the selected port is not implemented, all registers in the port status page are read as 0. Table 10−3.
Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. Fault 1 RW Fault.
10.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the PCI7x21/PCI7x11 controller, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10−7 shows the configuration of the vendor-dependent page, and Table 10−8 shows the corresponding field descriptions. Table 10−7.
10.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Table 10−9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 10−9.
10−8
11 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 flash media controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.
11.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h Read-only 104Ch 11.
11.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11−2 for a complete description of the register contents.
11.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See Table 11−3 for a complete description of the register contents.
11.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 01h, identifying the controller as a mass storage controller. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision is indicated in the least significant byte (00h). See Table 11−4 for a complete description of the register contents.
11.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no built-in self-test. See Table 11−6 for a complete description of the register contents.
11.9 Subsystem Vendor Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h (see Section 11.22). All bits in this register are reset by GRST only.
11.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Bit 7 6 5 4 Name Type Default 3 2 1 0 Interrupt line RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: Interrupt line 3Ch Read/Write FFh 11.
11.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core. Bit 7 6 5 Name Type Default 4 3 2 1 0 Minimum grant RU RU RU RU RU RU RU RU 0 0 0 0 0 1 1 1 Register: Offset: Type: Default: Minimum grant 3Eh Read/Update 07h Table 11−9. Minimum Grant Register Description BIT 7−0 FIELD NAME MIN_GNT TYPE DESCRIPTION RU Minimum grant.
11.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 11−11 for a complete description of the register contents.
11.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the flash media controller related to PCI power management. See Table 11−12 for a complete description of the register contents.
11.18 Power Management Control and Status Register The power management control and status register implements the control and status of the flash media controller. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 11−13 for a complete description of the register contents.
11.20 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the flash media controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 Name 4 3 2 1 0 Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Power management data 4Bh Read-only 00h 11.
11.22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 11−15 for a complete description of the register contents.
11.23 Diagnostic Register This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by the flash media cores. See Table 11−16 for a complete description of the register contents. All bits in this register are reset by GRST only.
11−16
12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 SD host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.
12.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h Read-only 104Ch 12.
12.3 Command Register The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 12−2 for a complete description of the register contents.
12.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See Table 12−3 for a complete description of the register contents.
12.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h, identifying the function as an SD host controller. The programming interface is 01h, indicating that the function is a standard SD host with DMA capabilities. Furthermore, the TI chip revision is indicated in the least significant byte (00h).
12.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the SD host controller. See Table 12−5 for a complete description of the register contents.
12.8 SD Host Base Address Register The SD host base address register specifies the base address of the memory-mapped interface registers for each standard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs is dependent on the number of SD sockets in the implementation See Table 12−7 for a complete description of the register contents.
12.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only.
12.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12−8, indicating that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.
12.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core. Bit 7 6 5 Name Type Default 4 3 2 1 0 Maximum latency RU RU RU RU RU RU RU RU 0 0 0 0 0 1 0 0 Register: Offset: Type: Default: Maximum latency 3Fh Read/Update 04h Table 12−10. Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 7−0 MAX_LAT RU Maximum latency.
12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 12−12 for a complete description of the register contents.
12.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the SD host controller related to PCI power management. See Table 12−13 for a complete description of the register contents.
12.19 Power Management Control and Status Register The power management control and status register implements the control and status of the SD host controller. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 12−14 for a complete description of the register contents.
12.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the SD host controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 Name 4 3 2 1 0 Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Power management data 87h Read-only 00h 12.
12.23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register contents.
12.25 Slot 0 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. Bit 7 6 RW RW RW RW RW 0 0 0 0 0 Name Type Default 5 4 3 2 1 0 RW RW RW 0 0 0 Slot 0 3.3-V maximum current Register: Type: Offset: Default: Slot 3.
12.28 Slot 3 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 3 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. If slot 3 is not implemented, this register is read-only and returns 0s when read. Bit 7 6 RW RW RW RW RW 0 0 0 0 0 Name Type Default 5 4 3 2 1 0 RW RW RW 0 0 0 Slot 3 3.
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13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 Smart Card controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.
13.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h Read-only 104Ch 13.
13.3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between other functions, and these control bits appear separately according to their software function. See Table 13−2 for a complete description of the register contents.
13.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See Table 13−3 for a complete description of the register contents.
13.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision is indicated in the least significant byte (00h). See Table 13−4 for a complete description of the register contents.
13.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no built-in self-test. See Table 13−6 for a complete description of the register contents.
13.9 Smart Card Base Address Register 1−4 Each socket has its own base address register. For example, a device supports three Smart Card sockets uses three base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2). These registers are used by this function to determine where to forward a memory transaction to the Smart Card Control and Communication Register sets.
13.11 Subsystem Identification Register This register is read-update and can be modified through the subsystem ID alias register. This register has no effect to the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM configuration. All bits in this register are reset by GRST only.
13.14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13−7, indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted. If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.
13.16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core. Bit 7 6 5 Name 4 3 2 1 0 Maximum latency Type Default RU RU RU RU RU RU RU RU 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Maximum latency 3Fh Read/Update 00h Table 13−9. Maximum Latency Register Description BIT FIELD NAME TYPE DESCRIPTION 7−0 MAX_LAT RU Maximum latency.
13.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the Smart Card controller related to PCI power management. See Table 13−11 for a complete description of the register contents.
13.19 Power Management Control and Status Register The power management control and status register implements the control and status of the Smart Card controller. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 13−12 for a complete description of the register contents.
13.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 Name 4 3 2 1 0 Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Power management data 4Bh Read-only 00h 13.22 General Control Register This register controls this function.
13.23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 13−14 for a complete description of the register contents.
13.25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register set. The software utilizes this information and adjusts the software and firmware behavior if necessary. Corresponding bits are tied to 0 if the socket is not implemented.
Table 13−15. Smart Card Configuration 1 Register Description BIT FIELD NAME TYPE 31−28 SCRTCH_PAD RW 27 CLASS_B_SKT3 R Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller, this bit is a read-only 0. 26 CLASS_B_SKT2 RW Socket 2 Class B Smart Card support. Since socket 2 is not implemented in the controller, this bit is a read-only 0. 25 CLASS_B_SKT1 RW Socket 1 Class B Smart Card support. When this bit is set to 1, socket 1 supports Class B Smart Cards.
13.26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set. The software utilizes this information and adjusts the software and firmware behavior, if necessary. See Table 13−16 for a complete description of the register contents. All bits in this register are reset by GRST only.
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14 Electrical Characteristics 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2.2 V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
Recommended Operating Conditions (continued) OPERATION 3.3 V PCIk 5V 3.3 V CardBus VIH† High-level input voltage 3.3 V 16-bit PC Card 5 V 16-bit PC(0−2) VO§ tt IO Input voltage Output voltage Input transition time (tr and tf) 2 2.4 0.6 SC_VCC_5V PCIk VI 2 0.475 VCC(A/B) 2 SC_DATA, SC_FCB, SC_RFU Low-level input voltage NOM 0.5 VCCP 0.7 VCC Miscellaneous‡ VIL† MIN 3.3 V 0 MAX UNIT VCCP VCCP VCC(A/B) VCC(A/B) VCC(A/B) VCC VCC SC_VCC_5V 0.3 VCCP 5V 0 0.8 3.3 V CardBus 0 0.
Recommended Operating Conditions (continued) OPERATION S100 operation Receive input jitter Receive input skew TPA, TPB cable inputs Between TPA and TPB cable inputs MIN NOM MAX UNIT ±1.08 S200 operation ±0.5 S400 operation ±0.315 S100 operation ±0.8 S200 operation ±0.55 S400 operation ±0.
14.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TERMINALS PCI VOH High-level output voltage PC Card OPERATION 0.9 VCC 5V 3.3 V CardBus IOH = −2 mA IOH = −0.15 mA 0.9 VCC 3.3 V 16-bit IOH = −0.15 mA 2.4 5 V 16-bit IOH = −0.15 mA 2.8 IOH = −4 mA 3.3 V VOL Low-level output voltage PC Card 5V 3.3 V 16-bit IOL = 0.7 mA 5 V 16-bit IOL = 0.
14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 14.4.1 Device PARAMETER VTH VO Power status threshold, CPS input† TEST CONDITION 400-kΩ resistor† TPBIAS output voltage At rated IO current II Input current (PC0−PC2 inputs) † Measured at cable power side of resistor. MIN MAX 4.7 7.5 V 1.665 2.015 V 5 µA VCC = 3.6 V UNIT 14.4.
14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature ALTERNATE SYMBOL PARAMETER tc tw(H) Cycle time, PCLK tw(L) tr, tf Pulse duration (width), PCLK low tw tsu Pulse duration (width), GRST Pulse duration (width), PCLK high Slew rate, PCLK Setup time, PCLK active at end of PRST TEST CONDITIONS MIN MAX UNIT tcyc thigh 30 ns 11 ns tlow ∆v/∆t 11 ns trst 1 ms 100 ms 1 trst-clk 4 V/ns 14.
15 Mechanical Information The PCI7x21/PCI7x11 device is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal lead (Pb atomic number 82) free MicroStar BGA package (ZHK). The following figure shows the mechanical dimensions for the GHK package. The GHK and ZHK packages are mechanically identical; therefore, only the GHK mechanical drawing is shown.
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