User’s Guide December 2002 SBAU077
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Contents 1 Introduction to the MSC1210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 MSC1210 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 MSC1210 Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.1 I/O Ports (P0, P1, P2, and P3) . . . . . . . . . . . . . . . . . . .
Contents 5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Events That Can Trigger Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 Enabling Interrupts . . . . . . . . . . . . . . . . . . . .
Contents 13 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . .
Contents 16 8052 Assembly Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3 Number Bases . . . . . . . . . . . . . . . . . . . . . .
Contents A Additional Features in the MSC1210 Compared to the 8052 . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Additional Features in the MSC1210 Compared to 8052 . . . . . . . . . . . . . . . . . . . . . . . . . A-2 B Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 MSC1210 Timing Chain and Clock Control Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1. 1−2. 1−3. 2−1. 2−2. 7−1. 7−2. 7−3. 7−4. 7−5. 7−6. 7−7. 8−1. 9−1. 9−2. 9−3. 9−4. 9−5. 9−6. 9−7. 9−8. 11−1. 11−2. 11−3. 11−4. 11−5. 11−6. 12−1. 12−2. 12−3. 12−4. 12−5. 12−6. 13−1. 13−2. 13−3. 13−4. 14−1. 14−2. MSC1210 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Pin Configuration of the MSC1210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 16−1. 17−1. 17−2. 17−3. 17−4. 17−5. 17−6. 17−7. 17−8. 17−9. 17−10. 17−11. 17−12. 17−13. 17−14. 17−15. 17−16. 17−17. 17−18. 17−19. 17−20. B−1. viii Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 Timer/Counter 0 − Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 Timer/Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1. 2−1. 2−2. 3−1. 5−1. 7−1. 8−1. 8−2. 8−3. 8−4. 9−1. 9−2. 9−3. 9−4. 9−5. 9−6. 10−1. 10−2. 10−3. 10−4. 10−5. 10−6. 10−7. 10−8. 10−9. 10−10. 10−11. 10−12. 10−13. 11−1. 11−2. 11−3. 11−4. 11−5. 12−1. 12−2. 12−3. 12−4. 12−5. Pin Descriptions of the MSC1210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Program and Data Memory Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 14−1. 14−2. 14−3. 16−1. 16−2. 16−3. 16−4. 17−1. C−1. x Typical Sub-Circuit Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Comparator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Band Gap Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter describes the basic function of the MSC1210 analog-to-digital converter (ADC). Topic Page 1.1 MSC1210 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 MSC1210 Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Enhanced 8051 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.
MSC1210 Description 1.1 MSC1210 Description The MicroSystem family of devices is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. They provide highperformance mixed signal solutions. The MicroSystem family not only includes high-end analog features and digital processing capability, but also integrates high-performance peripherals to offer a unique system solution.
MSC1210 Pin-Out The on-chip FLASH memory is programmable in a variety of modes over a wide temperature and operating voltage range. This greatly simplifies programming at both the manufacturing level and in the field. The on-chip high-performance analog features are state-of-the-art. The performance and features of the analog functions rival the best of the industry.
MSC1210 Pin-Out Table 1−1. Pin Descriptions of the MSC1210 Pin # Name Description 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN The crystal oscillator pin XIN supports parallel resonant AT cut crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. 3-10 P3.0-P3.7 Port 3 is a bidirectional I/O port.
MSC1210 Pin-Out Table 1−1 Pin Descriptions of the MSC1210 (Continued) Pin # Name Description 34-40, 43 P2.0-P2.7 Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Port 2—Alternate Functions: 34-40, 43 P2.0-P2.7 PORT ALTERNATE MODE P2.0 A8 Address Bit 8 P2.1 A9 Address Bit 9 P2.2 A10 Address Bit 10 P2.3 A11 Address Bit 11 P2.4 A12 Address Bit 12 P2.5 A13 Address Bit 13 P2.6 A14 Address Bit 14 P2.
MSC1210 Pin-Out Table 1−1 Pin Descriptions of the MSC1210 (Continued) Pin # Name Description 46, 47, 49-54 P0.0−P0.7 P0.5 AD5 Address/Data Bit 5 P0.6 AD6 Address/Data Bit 6 P0.7 AD7 Address/Data Bit 7 55, 56, 59−64 1.2.1 P1.0−P1.7 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Port 1—Alternate Functions: PORT ALTERNATE MODE P1.0 T2 T2 Input P1.1 T2EX T2 External Input P1.2 RxD1 Serial Port Input P1.3 TxD1 Serial Port Output P1.
MSC1210 Pin-Out 1.2.1.2 Port 1 Port 1 consists of eight I/O lines that may be used to interface to external parts. Port 1 is commonly used to interface to external hardware such as LCDs, keypads, and other devices. As opposed to a standard 8052 core, all I/O lines of the MSC1210 serve optional alternate functions, as described below. These lines can still be used for the developing purposes, if the functions described below are not needed. P1.0 (T2): If T2CON.
MSC1210 Pin-Out 1.2.1.3 Port 2 Like port 0, port 2 is dual-function. In some circuit designs, it is available for accessing external devices, while in others it is used to address external RAM or external code memory. When more than 256 bytes of external RAM are used, port 2 is used to output the high byte of the address that is to be accessed in a MOVX operation. Whether port 2 is used to address external memory or as general I/O lines is defined by the EGP23 bit in hardware configuration Register 1.
MSC1210 Pin-Out P3.2 (INT0): When so configured, this line is used to trigger an external 0 Interrupt. This may either be low-level triggered or may be triggered on a 1-0 transition (see Chapter 10, Interrupts, for details). You can assign any function to this pin as long as the circuit has no need to trigger an external 0 interrupt. P3.3 (INT1/TONE/PWM): When so configured, this line is used to trigger an external 1 Interrupt.
MSC1210 Pin-Out 1.2.3 Reset Line (RST) Pin 13 is the master reset line for the microcontroller. When this pin is brought high for two instruction cycles, the microcontroller is effectively reset. SFRs, including the I/O ports, are restored to their default conditions and the program counter is reset to 0000H. Keep in mind that Internal RAM is not affected by a reset. The microcontroller begins executing code at 0000H when pin 13 returns to a low state.
MSC1210 Pin-Out 1.2.6 External Access (EA) The external access (EA) line at pin 48 is used to determine whether the MSC1210 will execute your program from external code memory or from internal code memory. If EA is tied high (connected to supply), the microcontroller will execute the program it finds in internal/on-chip code memory. If EA is tied low (to ground), it will attempt to execute the program that it finds in the attached external program memory.
Enhanced 8051 Core 1.3 Enhanced 8051 Core The MSC1210 is an 8052-based family of high-performance, mixed-signal controllers. All instructions in the MSC1210 family perform exactly the same function as they would in a standard 8052 core. Although the effect on bits, flags, and registers is the same, the timing is different.
Family Device Compatibility 1.4 Family Device Compatibility The hardware functionality and pin outs across the MSC1210 family are fully compatible. The only difference between family members is the memory configuration and this enables simple migration between family members. Code written for the 4K bytes program memory version of the MSC1210 can be executed directly on the 8K, 16K, or 32K versions. This allows you to add or delete software functions and to freely migrate between family members.
High-Performance Peripherals 1.7 High-Performance Peripherals High-performance peripherals are included on-chip, which offload CPU processing and control functions from the core to further improve the overall device efficiency and throughput.
Chapter 2 This chapter defines the Memory Organization of MSC1210 ADC. Topic Page 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Internal RAM . . . . . . . . . . .
Description 2.1 Description The MCS1210 has three very general types of memory. To program the MCS1210 effectively, it is necessary to have a basic understanding of these memory types: - Special Function Registers refer to 128 bytes that control the operation of the MSC1210. - Program Memory is used to store the actual program that may reside on- chip, off-chip, or both. - Data Memory is static random access memory (SRAM) that can reside on-chip, off-chip, or both.
Program Memory For example, in the Y5 model there is 32k flash memory available. This 32k may be configured as either program memory, data memory, or both. This configuration is set at the moment the firmware is loaded onto the MSC1210 by setting hardware configuration register HCR0 as per Table 2−1. This table indicates the total amount of program and data memory available for each part revision given a specific HCR0 setting. Table 2−1. Program and Data Memory Size.
Data Memory Table 2−2. Program and Data Memory Addresses.
Data Memory On-chip extended static RAM provides 1k of data memory that requires no external circuitry and is available regardless of how the MSC1210’s flash memory is designated. This makes it a convenient memory area for purposes such as temporary buffers, calculation scratchpads, or any other purpose that requires 1k or less of memory, but does not require it to survive a power failure. 2.3.
Internal RAM Figure 2−2. MSC1210 Memory Map Register Bank. 2.4 Internal RAM As shown in Figure 2−2, the MSC1210 has a bank of 256 bytes of internal RAM. This internal RAM is found on-chip within the IC, so it is the fastest RAM available and is also the most flexible in terms of reading, writing, and modifying its contents. internal RAM is volatile, so when the MSC1210 is powered up, the contents of this memory bank is random.
Internal RAM 2.4.1 The Stack The stack is a “last in, first out” (LIFO) storage area that exists in internal RAM. It is used by the MSC1210 to store values that the user program manually pushes onto the stack, as well as to store the return addresses for CALLs and interrupt service routines (ISRs)—more on these topics later. The stack is defined and controlled by an SFR called SP.
Internal RAM But watch out! As the memory map shows, the MSC1210 has four distinct register banks. When the MSC1210 is first reset, register bank 0 (addresses 00H through 07H) is used by default. However, the MSC1210 may be instructed to use one of the alternate register banks (i.e., register banks 1, 2, or 3). In this case, R4 will no longer be the same as internal RAM address 04H.
Internal RAM As shown, bit memory is not really a new type of memory, it is just a subset of internal RAM. However, because the MSC1210 provides special instructions to access these 16 bytes of memory on a bit-by-bit basis, it is useful to think of it as a separate type of memory. Always keep in mind that it is just a subset of internal RAM, and that operations performed on internal RAM can change the values of the bit variables.
Internal RAM 2.4.4 Special Function Register (SFR) Memory SFRs are areas of memory that control specific functionality of the MSC1210. For example, four SFRs permit access to the 32 input/output lines (eight lines per SFR) of the MSC1210. Another SFR allows a program to read or write to the MSC1210 serial port. Other SFRs allow the user to set the serial baud rate, control and access timers, and configure the MSC1210 interrupt system. When programming, SFRs have the illusion of being internal memory.
Chapter 3 ! Chapter 3 defines the MSC1210 SFRs. Topic Page 3.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Referencing SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Bit-Addressable SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 SFR Types . . . . . . . . . . . . . . . . . . . . . . . .
Description 3.1 Description The MSC1210 is a flexible microcontroller with a relatively large number of modes of operation. Your program may inspect and/or change the operating mode of the MSC1210 by manipulating the values of its SFRs. SFRs are accessed as if they were normal internal RAM. The only difference is that internal RAM is addressed in direct mode with addresses 00H through 7FH, whereas SFR registers are accessed in the range of 80H through FFH. Each SFR has an address (80H−FFH) and a name.
Referencing SFRs 3.2 Referencing SFRs When writing code in assembly language, SFRs may be referenced either by their name or their address. For example, the SBUF0 SFR is at address 99H (see Table 3−1). In order to write the value 24H to the SBUF SFR in assembly language, it would be written in code as: MOV 99h,#24h This instruction moves the value 24H into address 99H. The value 99H is in the range of 80H to FFH, and, therefore, refers to an SFR.
Bit−Addressable SFRs 3.3 Bit−Addressable SFRs All SFRs that have addresses divisible by eight (i.e., 80H, 88H, 90H, 98H, etc.) are bit-addressable. This means that individual bits of these SFRs can be set or cleared using the SETB and CLR instruction. Note: The SFRs whose names appear BOLD in Table 3−1 are SFRs that may be accessed via bit operations; these also happen to be the first column of SFRs on the left side of the chart. The other SFRs cannot be accessed using bit operations such as SETB or CLR.
SFR Definitions 3.5 SFR Definitions This section will endeavor to quickly overview each of the SFRs found in the SFR chart map of Table 3−1. It is not the intention of this section to fully explain the functionality of each SFR—this information will be covered in separate chapters. This section is to just give a general idea of what each SFR does. P0 (Port 0, Address 80H, Bit-Addressable): This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller.
SFR Definitions DPL0/DPH0 (Data Pointer 0 Low/High, Addresses 82H/83H): The SFRs DPL0 and DPH0 work together to represent a 16-bit value called Data Pointer 0. The data pointer is used in operations regarding external RAM and some instructions involving code memory. It can represent values from 0000H to FFFFH (0 through 65,535 decimal) because it is an unsigned 2-byte integer value, Note: DPTR is really DPH0 and DPL0 taken together as a 16-bit value.
SFR Definitions TMOD (Timer Mode, Address 89H): This SFR is used to configure the mode of operation of each of the two timers. Using this SFR, the program may configure each timer to be a 16-bit timer, an 8-bit auto-reload timer, a 13-bit timer, or two separate timers. Additionally, the timers may be configured to only count when an external pin is activated or to count events that are indicated on an external pin.
SFR Definitions MPAGE (Memory Page, Address 92H): This SFR contains the high byte of the address to access when using the MOVX @Ri instructions. A normal 8052 requires the high byte of the address be written to P2; the MSC1210, however, requires that the byte be written to the MPAGE SFR. CADDR (Configuration Address Register, Address 93H): This SFR is used to read the 128 bytes of Flash hardware configuration data.
SFR Definitions SPIRCON (SPI Receive Control, Address 9CH): This SFR is dual-purpose: when read, it will return the number of bytes currently in the SPI receive buffer; when written, it can be used to clear the receive buffer and/or indicate how many characters should accumulate in the receive buffer before triggering an SPI interrupt.
SFR Definitions AISTAT (Auxiliary Interrupt Status, Address A7H): This is a read-only SFR that will provide you with the current status of all the enabled (not masked by AIE) auxiliary interrupts. Those interrupts that have been disabled (masked) by AIE will not be available in AISTAT. IE (Interrupt Enable, Address A8H): This SFR is used to enable and disable specific interrupts.
SFR Definitions SCON1 (Serial Control 1, Address C0H, Bit-Addressable): This SFR is used to configure the behavior of the MSC1210 secondary onboard serial port. SCON1 controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received. SBUF1 (Serial Buffer 1, Address C1H): This SFR is used to send and receive data via the secondary onboard serial port.
SFR Definitions ADCON0/ADCON1 (ADC Control 0 and 1, Addresses DCH/DDH): These two SFRs allow the user program to configure various aspects of the ADC. ADCON2/ADCON3 (ADC Controls 2 and 3, Addresses DEH/DFH): These two SFRs control the decimation rate of the ADC; in other words, they control the frequency at which sampled data will be provided to the user program via the ADRES SFRs.
SFR Definitions FTCON (Flash Memory Timing Control, Address EFH): This SFR controls the timing and period of flash memory, specifically for writing and erasing flash memory. The period of writing to flash memeory is determined by USEC and the low four bits of FTCON, and should produce a write period of 30µs to 40µs. Meanwhile, the period of erasing flash memory is determined by MSECH/MSECL and the high four bits of FTCON, and should produce an erase period of 4ms to 11ms.
SFR Definitions MSINT (Milliseconds Interrupt, Address FAH): This SFR can be set to cause an interrupt to occur after the specified number of milliseconds. This assumes that the millisecond registers FCH and FDH are set to generate a cycle every millisecond. The precise frequency at which MSINT will cause an interrupt depends on the system clock and the value of the MSECH, MSECL, and MSINT SFRs.
Chapter 4 " Chapter 4 describes the basic register functions of the MSC1210 ADC. Topic Page 4.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 R Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4 B Register . . . . . . . .
Description 4.1 Description A number of MSC1210 registers can be considered basic. Very little can be done without them and a detailed explanation of each one is warranted to make sure the reader understands these registers before getting into more complicated areas of development. 4.2 Accumulator The accumulator is a familiar concept when working with any assembly language. The accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions.
B Register As mentioned previously, there are four sets of R registers: register bank 0, 1, 2, and 3. When the MSC1210 is first powered up, register bank 0 (addresses 00H through 07H) is used by default. In this case, for example, R4 is the same as internal RAM address 04H. However, yours program may instruct the MSC1210 to use one of the alternate register banks (i.e., register banks 1, 2, or 3). In this case, R4 will no longer be the same as internal RAM address 04H.
Data Pointer (DPTR0/DPTR1) 4.6 Data Pointer (DPTR0/DPTR1) The data pointer (DPTR0/DPTR1) is the user-accessible 16-bit (2-byte) register of the MSC1210. The accumulator, R registers, and B register are all 1-byte values. The PC just described is a 16-bit value, but is not directly user-accessible as a working register. DPTR0/DPTR1, as the name suggests, are used to point to data. They are used by a number of commands that allow the MSC1210 to access data and code memory.
Chapter 5 # Chapter 5 describes the various addressing modes of the MSC1210. Topic Page 5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4 Indirect Addressing . . . . . . . . . . . . . .
Description 5.1 Description As is the case with all microcomputers from the PDP-8 onwards, the MSC1210 uses several memory addressing modes. An addressing mode refers to how you are accessing (addressing) a given memory location or data value. In summary, the addressing modes are listed in Table 5−1 with an example of each. Table 5−1. MSC1210 Addressing Modes.
Direct Addressing 5.3 Direct Addressing Direct addressing is so named because the value to be stored in memory is obtained by directly retrieving it from another memory location. For example: MOV A,30h This instruction will read the data out of internal RAM address 30H (hex) and store it in the accumulator (A). Direct addressing is generally fast because, although the value to be loaded is not included in the instruction, it is quickly accessible due to it being stored in the MSC1210 internal RAM.
Indirect Addressing 5.4 Indirect Addressing Indirect addressing is a very powerful addressing mode that in many cases provides an exceptional level of flexibility. Indirect addressing is also the only way to access the upper 128 bytes of Internal RAM found on an 8052. Indirect addressing appears as follows: MOV A,@R0 This instruction causes the MSC1210 to analyze the value of the R0 register.
External Direct Addressing 5.5 External Direct Addressing External memory is accessed using a suite of instructions that use external direct addressing. It is referred to as external direct because it appears to be direct addressing, but it is used to access external memory rather than internal memory. There are only two commands that use external direct addressing mode: MOVX A,@DPTR MOVX @DPTR,A As you can see, both commands use DPTR.
External Indirect Addressing 5.6 External Indirect Addressing External memory can also be accessed using a form of indirect addressing called external indirect. This form of addressing is usually only used in relatively small projects that have a very small amount of external RAM. An example of this addressing mode is: MOVX @R0,A Once again, the value of R0 is first read and the value of the accumulator is written to that address in external RAM, internal extended SRAM, and internal flash data memory.
Chapter 6 $ % Chapter 6 describes the program flow of the MSC1210 ADC. Topic Page 6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Conditional Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3 Direct Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.4 Direct Calls . . . . . . . . . . . . . . . . . . . . . .
Description 6.1 Description When the MSC1210 is first initialized the PC SFR is cleared to 0000H. The part then begins to execute instructions sequentially in memory unless a program instruction causes the PC to be otherwise altered. There are various instructions that can modify the value of the PC; specifically, conditional branching instructions, direct jumps and calls, and returns from subroutines.
Direct Jumps Consider the example: LJMP NEW_ADDRESS . . . NEW_ADDRESS: .... The LJMP instruction in this example means “Long Jump.” When the MSC1210 executes this instruction, the PC is loaded with the address of NEW_ADDRESS and program execution continues sequentially from there.
Direct Calls 6.4 Direct Calls Another operation that will be familiar to seasoned programmers is the LCALL instruction. This is similar to a “GOSUB” command in Basic. When the MSC1210 executes an LCALL instruction, it immediately pushes the current PC onto the stack and then continues executing code at the address indicated by the LCALL instruction. 6.
Chapter 7 Chapter 7 describes the system timing of the MSC1210 ADC. Topic Page 7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 System Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3 Startup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 7.1 Description In order to understand—and better make use of—the MSC1210, it is necessary to understand some underlying information concerning timing. The MSC1210 operates with timing derived from an external crystal or a clock signal generated by some other system. A crystal is a mechanical oscillator that allows an electronic oscillator to run at a very precisely known frequency. One can find crystals of virtually any frequency depending on the application requirements.
Description An instruction cycle is, in reality, four clock cycles. That is to say, if an instruction takes one instruction cycle to execute, it will take four clocks from a crystal or oscillator to execute. Using the maximum crystal frequency of 33MHz, the crystal oscillates 33 000 000 times per second.
System Timers 7.2 System Timers In addition to the standard 8052 timers to be described in Chapter 8, the MSC1210 includes the following system timers, both of which are capable of triggering an auxiliary interrupt (for more on interrupts, see chapter 10): - Microseconds Timer: set via the USEC (FBH) SFR, and is used to configure the flash writing timing and also used by the PWM module.
System Timers Figure 7−2. MSC1210 Timing Chain and Clock Control Figure 7−3.
System Timers 7.2.1 Microseconds Timer The microseconds timer is used by the MSC1210 in order to establish a 1µs clock. This clock, in turn, is used by flash memory to establish timing for flash writes, as well as by the PWM module. The USEC (FBH) SFR should be set to a value such that the system clock divided by the value of this SFR, plus one, generates a 1µs clock. For example, given a system clock of 12.000MHz, USEC should be set to: 12 000 000/1 000 000 = 12 – 1 = 11. Therefore, for a 12.
System Timers Figure 7−4. System Timing Interrupt Control The MSECH (FDH) and MSECL (FCH) SFRs should be set to a value such that the system clock divided by the value of these SFRs, plus one, generates a 1ms clock. For example, given a system clock of 12.000MHz, MSECH/MSECL should be set to 12 000 000 / 1000 = 12 000 – 1 = 11 999. Thus, for a 12.000MHz system clock, MSECH/MSECL should be set to 11 999 to generate a 1ms clock.
System Timers 7.2.2.2 One Hundred Millisecond Clock The one hundred millisecond clock is used by the MSC1210 in order to establish a 10Hz clock. This clock is not directly outputted by the MSC1210; it is used as the input into the seconds auxiliary interrupt and also is used by the watchdog timer.
Startup Timing 7.3 Startup Timing When power is turned on, or a reset is initiated, a power-on delay circuit is implemented with a 17-bit counter to guarantee that the power supply has reached a certain level, and the oscillator is stable. The delay introduced by this counter is: 24MHz System clock: (217 − 1) S (1/24) S 10−6 = 0.005461s 1MHz System clock: (217 − 1) S 10−6 = 0.131071s 7.3.1 Normal-Mode Power-On Reset Timing EA is sampled during power-on reset for code security purposes.
Startup Timing Figure 7−7. Serial Flash Programming Power-On Timing (EA is ignored) Table 7−1. Signal Definitions for Reset Timing Diagrams Symbol Parameter Min Max Unit trw RST Width 10 tCLK(1) — ns trrd RST rise to PSEN ALE internal pull high — 5 µs trfd RST falling to PSEN and ALE start — (217+512) tCLK(1) ns trs Input signal to RST falling setup time tCLK(1) — ns (217+512) tCLK(1) — ns trh Notes: 7-10 RST falling to input signal hold time 1) tCLK is the Xtal clock period.
Chapter 8 Chapter 8 describes the timers of the MSC1210 ADC. Topic Page 8.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 How Does a Timer Count? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 Using Timers to Measure Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4 Using Timers as Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 8.1 Description The MSC1210 comes equipped with three standard timer/counters, all of which may be controlled, set, read, and configured individually. The timer/counters have three general functions: 1) Keeping time and/or calculating the amount of time between events 2) Counting the events themselves 3) Generating baud rates for the serial port The uses of the three timer/counters are distinct, so we will talk about each of them separately.
Using Timers to Measure Time The individual bits of TMOD have the following functions: SFR 8EH 7 6 5 4 3 2 1 0 Reset Value 0 0 T2M T1M T0M MD2 MD1 MD0 01H T2M (bit 5)—Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This bit has no effect on instruction cycle timing.
Using Timers to Measure Time Unlike instructions—some of which require one instruction cycle, others 2, and others 4—the timers are consistent. They will always be incremented once every 12 (or four) clocks. Therefore, if a timer has counted from 0 to 55 000 you may calculate: 55 000 / 2 750 000 = 0.020 seconds (fosc/12) or 55 000 / 8 250 000 = 0.007 seconds (fosc/4) The trade off in using fosc/12 or fosc/4 as the clock source is (1) code compatibility and (2) resolution.
Using Timers to Measure Time It is apparent that the maximum value a timer may have is 65,535 because there are only two bytes devoted to the value of each timer. If a timer contains the value 65,535 and is subsequently incremented, it will reset—or overflow—back to 0. 8.3.3 TMOD SFR The TMOD SFR is used to control the mode of operation of both timers. Each bit of the SFR gives the microcontroller specific information concerning how to run a timer.
Using Timers to Measure Time As is shown in the previous chart, four bits (two for each timer) are used to specify a mode of operation. The modes of operation are shown in Table 8−2. Table 8−2. Timer Modes and Usage TxM1 TxM0 Timer Mode 0 0 0 0 1 1 1 Description of Timer Mode Timer 1 Timer 0 13-bit timer/counter Y Y 1 16-bit timer/counter Y Y 0 2 8-bit timer/counter with auto-reload Y Y 1 3 Two 8-bit counters (split timer mode) N Y The TMOD.
Using Timers to Measure Time When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is incremented from 31, it will roll over to 0 and overflow into THx, thus incrementing it. Therfore, only 13 bits of the two timer bytes are being used: bits 0 to 4 of TLx, and bits 0 to 7 of THx. This also means the timer can only contain 8192 values. If you set a 13-bit timer to 0, it overflows back to zero 8192 instruction cycles later.
Using Timers to Measure Time As shown, the value of TH0 never changed. In fact, when mode 2 is used, THx is almost always set to a known value and TLx is the SFR that is constantly incremented. THx is initialized once, and then left unchanged. The benefit of auto-reload mode is that, perhaps, the timer may need to always have a value from 200 to 255. When using mode 0 or 1, the code would have to be checked to see if the timer had overflowed and, if so, the timer reset to 200.
Using Timers to Measure Time So far, only four of the eight bits have been defined. That is because the other four bits of the SFR do not have anything to do with timers—they have to do with interrupts and they will be discussed in Chapter 10, Interrupts. Table 8−4 contains the bit address column because this SFR is bit-addressable.
Using Timers to Measure Time However, when dealing with a 13-bit or 16-bit timer, the chore is a little more complicated. Consider what happens when the low byte of the timer is read as 255, then the high byte of the timer is read as 15. In this case, what actually happens is that the timer value is 14/255 (high byte 14, low byte 255) but the readout is 15/255. The reason for this is because the low byte was read as 255.
Using Timers to Measure Time This approach can be used to cause the program to execute a fixed delay. As shown earlier, we calculated that it takes the 8051 1/20th of a second to count from 0 to 46 080. However, the TFx flag is set when the timer overflows back to 0. Therefore, to use the TFx flag to indicate when 1/20th of a second has passed, the timer must be set initially to 65 536 less 46 080, or 19 456. If the timer is set to 19 456, 1/20th of a second later the timer will overflow.
Using Timers as Event Counters 8.4 Using Timers as Event Counters We have discussed how a timer can be used for the obvious purpose of keeping track of time. However, the MSC1210 also allows the use of timers to count events. This can be useful in many applications. For example, a sensor is placed across a road that would send a pulse every time a car passes over it. This could be used to determine the volume of traffic on the road.
Using Timer 2 It is important to note that the MSC1210 checks the P3.4 line each instruction cycle (4 clock cycles). This means that if P3.4 is low, goes high, and goes back low in 3 clock cycles, it will probably not be detected by the MSC1210. This also means the MSC1210 event counter is only capable of counting events that occur at a maximum of 1/8th the rate of the crystal frequency. That is to say, if the crystal frequency is 12.000MHz, it can count a maximum of 1 500 000 events per second (12.
Using Timer 2 TR2 (bit 2)—Timer 1 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. C/T (bit 1)—Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode. 0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5).
Using Timer 2 8.5.3 Timer 2 in Capture Mode A new mode, specific to Timer 2, is called capture mode. As the name implies, this mode captures the value of Timer 2 (TH2 and TL2) into the capture SFRs (RCAP2H and RCAP2L). To put Timer 2 in capture mode, CP/RL2 (T2CON.0) and EXEN2 (T2CON.3) must be set. When configured as mentioned above, a capture occurs whenever a 1-0 transition is detected on T2EX (P1.1).
Using Timer 2 8.5.4 Timer 2 as a Baud Rate Generator Timer 2 can be used as a baud rate generator. This is accomplished by setting either RCLK (T2CON.5) or TCLK (T2CON.4). With Timer 1, the receive and transmit baud rate must be the same. With Timer 2, however, the user can configure the serial port to receive at one baud rate and transmit at another.
Chapter 9 Chapter 9 describes serial communication using the MSC1210 ADC. Topic Page 9.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 Setting the Serial Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 Setting the Serial Port Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4 Writing to the Serial Port . . . . . . . . . . . . . . . .
Description 9.1 Description The MSC1210 family has three serial port interfaces: two UARTs and one SPI. This chapter will cover the UARTs, while the SPI will be covered Chapter 13, Serial Peripheral Interface (SPI). One of the many powerful features of the MSC1210 is its integrated UARTs, otherwise known as universal synchronous/asynchronous receiver/transmitters.
Setting the Serial Port Mode 9.2 Setting the Serial Port Mode The first thing to be done when using the MSC1210 integrated serial port is, obviously, to configure it. This lets you tell the MSC1210 how many data bits are needed, the baud rate to be used, and how the baud rate will be determined. First, the Serial Control 0 (SCON0) SFR is presented and what each bit of the SFR represents is defined. Remember, SCON1 has the exact same function but relates to the secondary UART.
Setting the Serial Port Mode TI_0 (bit 1)—Transmitter Interrupt Flag. This bit indicates that data in the Serial Port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the eighth data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 (bit 0)—Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the Serial Port 0 buffer.
Setting the Serial Port Mode The high four bits (bits 4 through 7) are configuration bits. The bit REN means receiver enable. This bit is very straightforward; if data need to be received via the serial port, set this bit. This bit will almost always need to be set because leaving it cleared will prevent the MSC1210 from receiving serial data. The function of the SM2 bit depends on the serial mode. In mode 0, the SM2 bit is used to set the baud rate.
Setting the Serial Port Mode Figure 9−1. Serial Port 0 Mode 0 Transmit Timing—High Speed Operation. Figure 9−2. Serial Port Mode 0 Receive Timing—High Speed Operation. 9.2.2 Serial Mode 1: Asynchronous Full-Duplex In mode 1, serial data transfers are 10 bits long, full-duplex, and asynchronous. The transfer begins with a start bit, followed by eight bits of data (LSB first), then a stop bit. On receive, the stop bit is shifted into the RB8 bit in the SCON register.
Setting the Serial Port Mode Figure 9−3. Serial Port Mode 1 Transmit Timing. Figure 9−4. Serial Port 0 Mode 1 Receive Timing. Reception is enabled by configuring SCON0.RBN = 1. Reception of the data begins at the falling edge of start-bit detection. The RXDx pin is sampled 16 times-per-bit for any baud rate setting. When the falling edge of the start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover with the bit boundaries.
Setting the Serial Port Mode The baud rate is adjustable and is based on either Timer 1 or Timer 2. Serial Port 0 can use either Timer 1 or Timer 2, while Serial Port 1 can use only Timer 1. On an overflow from the timer, a clock is sent to the baud clock. The clock is divided by 16 to generate the baud clock. The PCON.SMOD0 and EICON.SMOD1 bits determine whether or not to divide Timer 1 by the rollover rate of 2.
Setting the Serial Port Mode The divide-by-32 is a result of the fOSC being divided by 2 (by setting T2CON.TCLK and T2CON.RCLK) and the Timer 2 overflow being divided by 16. To determine the RCAP2H:RCAP2L value from a given baud rate use the equation below: RCAP2H : RCAP2L + (65536 * f OSC ) 32 @ BaudRate Table 9−3. Common Baud Rates Using Timer 2 9.2.3 Baud Rate C/T2 RCAP2H:RCAP2L (@ 11.0592MHz fOSC) 57.6k 0 0FFFAH 19.2k 0 0FFEEH 9.6k 0 0FFDCH 4.8k 0 0FFB8H 2.4k 0 0FF70H 1.
Setting the Serial Port Mode Figure 9−6. Serial Port 0 Mode 2 Receive Timing. Transmission is initiated by any instruction that writes to SBUF. The transmission begins after the first rollover of the divide-by-16 counter after the write. The SCONx.Ti_x interrupt flag is set when the stop bit has been placed on the TXDx pin. Reception is enabled by configuring SCON0.RBN = 1. Reception of the data begins at the falling edge of start-bit detection.
Setting the Serial Port Mode 9.2.4 Serial Mode 3: Asynchronous Full-Duplex In mode 3, serial data transfers are 11 bits, full-duplex, and asynchronous. Mode 3 is identical to mode 2, with the exception of the baud rate. The transfer begins with a start bit, followed by eight bits of data (LSB first), an additional bit of data (ninth bit), and then a stop bit. On transmit, the ninth data bit is set by TB8. On receive, the ninth bit is shifted into the RB8 bit in the SCON register and the stop bit ignored.
Setting the Serial Port Mode Reception is enabled by configuring SCON0.RBN = 1. Reception of the data begins at the falling edge of start-bit detection. The RXDx pin is sampled 16 times per bit for any baud rate setting. When the falling edge of the start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover with the bit boundaries.
Setting the Serial Port Baud Rate 9.3 Setting the Serial Port Baud Rate Once the serial port mode has been configured, as explained above, the program must configure the serial port baud rate. In mode 0, the baud rate is either the clock frequency divided by 12 or the clock frequency divided by 4, depending on the SM2 bit in the SCONx register. Table 9−4 shows some commonly used baud rates for Mode 0. Table 9−4. Mode 0 Commonly Used Baud Rates.
Setting the Serial Port Baud Rate For example, with an 11.059MHz crystal, to configure the serial port to 19 200 baud, try plugging it in the first equation: TH1 = 256 − ((Crystal / 384) / Baud) TH1 = 256 − ((11 059 000 / 384) / 19 200) TH1 = 256 − ((28 799) / 19 200) TH1 = 256 − 1.5 = 254.5 As shown, to obtain 19 200 baud with an 11.059MHz crystal, TH1 would have to be set to 254.5. If it is set to 254, 14 400 baud is achieved and if it is set to 255, 28 800 baud is achieved.
Writing to the Serial Port Table 9−6. Baud Rate Settings for Timer 2. 33MHz clk 25MHz clk 11.0592MHz clk Baud Rate (kb/s) C/T2 RCAP2H RCAP2L RCAP2H RCAP2L RCAP2H RCAP2L 19.2 0 FFH EEH FFH F2H FFH FAH 9.6 0 FFH CAH FFH D7H FFH EEH 4.8 0 FFH 95H FFH AFH FFH DCH 2.4 0 FFH 29H FFH 5DH FFH B8H 1.2 0 FEH 52H FEH BBH FFH 70H 1.2 0 FCH A5H FDH 75H FEH E0H 9.
Reading the Serial Port 9.5 Reading the Serial Port Reading data received by the serial port is equally easy. To read a byte from the serial port, just read the value stored in the SBUF0 (99H) SFR after the MSC1210 has automatically set the RI flag in SCON.
Chapter 10 Chapter 10 describes the interrupts of the MSC1210 ADC. Topic Page 10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Events That Can Trigger Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 Enabling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.4 Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 10.1 Description As the name implies, an interrupt is some event that interrupts normal program execution. As stated previously, program flow is always sequential, being altered only by those instructions that expressly cause program flow to deviate in some way. However, interrupts give us a mechanism to put on hold the normal program flow, execute a subroutine, and then resume normal program flow as if we had never left it.
Events That Can Trigger Interrupts Thus, every 65 536 instruction cycles, Timer 0 overflows and the CPL and RETI instructions are executed. Those two instructions together require three instruction cycles, and accomplish the same goal as the first example. As far as the toggling of P3.0 goes, the code is 437 times more efficient! Not to mention it is much easier to read and understand because the timer 0 flag does not have to be checked in the main program.
Events That Can Trigger Interrupts In other words, the MSC1210 can be configured so that any of the events in Table 10−1, ranging from a simple Timer 0 overflow to a watchdog or ADC conversion event, will trigger an interrupt calling the appropriate interrupt handler routines. Interrupt/Event—The first column of Table 10−1 indicates the name of the event, or interrupt, in question.
Enabling Interrupts 10.3 Enabling Interrupts By default, at power-up all interrupts are disabled. This means that even if, for example, the TF0 bit is set, the MSC1210 will not execute the Timer 0 interrupt. You must specify in code which interrupts you want the MSC1210 to enable. You may enable and disable interrupts by modifying the IE (A8H), EICON (D8H), and EIE (E8H) SFRs, as shown in Table 10−2, Table 10−3, and Table 10−4. Table 10−2.
Polling Sequence Each of the MSC1210 interrupts has its own enable bit in one of these three SFRs. Enable a given interrupt by setting the corresponding bit. For example, to enable the Timer 1 Interrupt, execute either: MOV IE,#08h or SETB ET1 Both of the previous instructions set bit 3 of IE, thus enabling the Timer 1 Interrupt.
Interrupt Priorities 10.5 Interrupt Priorities The MSC1210 offers three levels of interrupt priority: highest, high, and low. By using interrupt priorities, higher priority may be assigned to certain interrupt conditions. The highest priority is reserved for the auxiliary interrupt that vectors through address 0033H—the auxiliary interrupt is always of highest priority and no other interrupt may be assigned that priority. All other interrupts may be assigned either high or low priority.
Interrupt Triggering When considering interrupt priorities, the following rules apply: 1) Nothing can interrupt the highest-priority auxiliary interrupt, not even another auxiliary interrupt. 2) Only an auxiliary interrupt (highest priority) can interrupt a high-priority interrupt. 3) A high-priority interrupt may interrupt a low-priority interrupt. 4) A low-priority interrupt may only occur if no other interrupt is currently executing.
Types of Interrupts 10.8 Types of Interrupts Each interrupt can be categorized as one these types: serial, external, timer, watchdog, or auxiliary. 10.8.1 Serial Interrupts There are two interrupt flags that provoke a serial interrupt: receive interrupt (RI) and transmit interrupt (TI). If either flag is set, a serial interrupt is triggered. As discussed in section 9.2, the RI bit is set when a byte is received by the serial port and the TI bit is set when a byte has been sent.
Types of Interrupts Note: Level-sensitive interrupts are not latched. If the interrupt is level-sensitive, the condition must be present until the processor can respond to it. This is most important if other interrupts are being used with a higher or equal priority. If the device is currently processing another interrupt of higher priority, the condition must be present until the current interrupt is complete.
Types of Interrupts 10.8.3 Timer Interrupts The MSC1210 microcontroller incorporates three 16-bit programmable timers, each of which can generate an interrupt. In addition, there are three other sources for timer interrupts: the milliseconds timer, seconds timer, and watchdog timer. Each timer has an independent interrupt enable, flag, vector, and priority. Timers 0, 1, and 2 set their respective flags when their individual timer overflows. These flags will be set regardless of the interrupt enable status.
Types of Interrupts Table 10−8.
Types of Interrupts The AISTAT (A7H) is a read-only SFR that returns the current state of interrupt conditions that are enabled. Any condition that is configured to provoke an interrupt and is currently true will return a 1. Any condition that is not currently true or was not configured to provoke an interrupt will return a 0. Table 10−10.
Types of Interrupts The four bits, PAI0 through PAI3, make up a 4-bit value that indicates the auxiliary interrupt that triggered the actual interrupt. Because the value returned by PAI is between 0 and 8, it can be used as an index or offset to determine what ISR to execute. There is no priority to the aquxiliary interrupts, but there is a priority to how they are displayed in the PAI register. Table 10−12.
Waking Up from Idle Mode a millisecond interrupt will be provoked every 20ms. This assumes and requires that MSECH (FDH) and MSECL (FCH) are set to values that represent a millisecond. If MSECH and MSECL are set to other values, the frequency at which the millisecond interrupt occurs will vary proportionally. The seconds interrupt functions in a manner similar to the millisecond interrupt, but can be used to provoke an interrupt at reduced frequencies, on the order of seconds.
Register Protection 10.10 Register Protection One very important rule applies to all interrupt handlers: interrupts must leave the processor in the same state as it was in when the interrupt initiated. Remember, the idea behind interrupts is that the main program is not aware that they are executing in the background.
Register Protection The guts of the interrupt are the MOV instruction and the ADD instruction. However, these two instructions modify the accumulator (the MOV instruction) and also modify the value of the carry bit (the ADD instruction will cause the carry bit to be set). The routine pushes the original values onto the stack using the PUSH instruction because an interrupt routine must ensure that the registers remain unchanged by the routine. It is then free to use the registers it protected as needed.
Common Problems with Interrupts 10.11 Common Problems with Interrupts Interrupts are a very powerful tool available to you, but when used incorrectly, can be a source of a huge number of debugging hours. Errors in interrupt routines are often very difficult to diagnose and correct.
Chapter 11 $ & ' ( Chapter 11 describes the pulse width modulator/tone generator of the MSC1210 ADC. Topic Page 11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Tone Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 11.1 Description The pulse width modulator (PWM) has two modes: one mode functions as a tone generator and the the other mode functions as a pulse width modulator. Figure 11−1. Block Diagram The PWM/tone generator is controlled and configured by a number of SFRs, the primary being the PWM Configuration (PWMCON, A1H) SFR. The individual bits of PWMCON have the following functions: SFR A1H 7 6 5 4 3 2 1 0 Reset Value — — PPOL PWMSEL SPDSEL TPCNTL.2 TPCNTL.1 TPCNTL.
Tone Generator The three bits that together make up TPCNTL, control the function of the PWM/ tone generator. The function of the generator is determined according to the table above. TPCNTL.0 enables or disables the PWM/tone generator. If set to ‘1’, the block will act as either a PWM or tone generator depending on the setting of TPCNTL.1. When TPCNTL.0 is ‘0’, the function block is completely disabled. This state of the block is the default state. When TPCNTL.
Tone Generator 11.2.1 Tone Generator Waveforms When TPCNTL[1:0] = 11, the output of the tone generator may be either a staircase waveform or a square waveform depending on the configuration of TPCNTL.2. When TPCNTL.2 is 1, a staircase waveform is generated that will have three levels: DGND, tristate, and VDD volts. When the TPCNTL.2 is 0, a square waveform of 50% duty cycle is generated that will have two levels: DGND and VDD volts. 11.2.1.1 Staircase Mode When TPCNTL.2 is 1 (i.e.
PWM Generator 11.3 PWM Generator The PWM generator is activated when TPCNTL[1:0] = 01. This setting allows a PWM waveform to be generated automatically by the MSC1210 with characteristics defined by the user program. The PWM is configured based on the PWMCON SFR, the PWM Period and PWM Duty settings, and the USEC SFR setting. The USEC SFR or SYS clock (defined by Speed Select) generates a tick that defines the unit period that is used by PWM Period and PWM Duty in defining the waveform.
PWM Generator Figure 11−5. Timing Diagram of a PWM Waveform In the timing diagram of a PWM waveform in Figure 11−5, the waveform is low for 2 ticks and high for 4 ticks. Thus, the value of PWM Period = 5 (6 ticks minus 1) and PWM Duty = 1 (2 ticks minus 1). Assuming the PPOL (PWMCON.5) bit is set, the actual length of a tick is defined by the value of USEC, or equal to the period of CLK. Configuring the PWM generator requires that the PWM Period and PWM Duty registers be set.
PWM Generator This can be expressed in code as: PWMCON = 0x10; // Sel PWM Duty Register PWM = 128−1; // PWM toggle at a count of 128 PWMCON = 0x09; // Sel PWM Period access, SysClk rate, PWM mode PWM = 512−1; // 11.0592MHz/512=21.6KHz PWM Freq, Period=512 counts Note: The port pin used for PWM (P3.3) must be configured as either standard 8051 or CMOS output for the tone generator/PWM to function.
PWM Generator 11.3.1 Example of PWM Tone Generation Table 11−2 illustrates configuring the PWM for tone generation, and Table 11−3 explains selected statements. Table 11−2. Configuring the PWM for Tone Generation Stmt 1 ‘C’ Source Code // PWM Assembly Source Code PUBLIC main RSEG ???main?PWM 2 3 4 5 6 7 8 9 10 11 #include #define OneUsConst (2−1) sbit p33=p3^3; void main(void) { PDCON &= 0xED; // turn on tone gen & sys timer USEC = OneUsConst; P33 = 1; // turn on P3.
PWM Generator 11.3.2 Example of PWM Tone Generation Idling When PWM is idling, system requirements for the PWM output varies (idle at low or high voltage). The output of P3.3 (Tone/PWM) is internal pull-high upon power-on reset—idle high. If idle low is needed, many methods can be used to initialize P3.3 to low. Note: If idle low on Tone/PWM is achieved by writing 0 to P3.3 (which will suppress PWM output), subsequently, writing a 1 to P3.3 will enable PWM output at any position of the PWM cycle.
PWM Generator Table 11−4. Configuring the PWM for Tone Generation with PWM Idling Stmt 1 ‘C’ Source Code // PWM Assembly Source Code PUBLIC main RSEG ???main?PWM 2 3 4 5 6 7 8 9 10 11 #include #define OneUsConst (2−1) sbit p33=p3^3; void main(void) { PDCON &= 0xED; // turn on tone gen & sys timer USEC = OneUsConst; P33 = 1; // turn on P3.
PWM Generator 11.3.3 Example of Updating PWM Both PWM Period and PWM Duty, set via the PWMHI and PWMLOW SFRs, are double-buffered. Their values are loaded to the 16-bit down counter and 16-bit PWMTemp register, respectively, when the counter expires. PWM Period and PWM Duty may be renewed anytime during a PWM cycle. The newly updated values are effective on the next PWM cycle. Double−buffered operation is depicted in Figure 11−6. PWM Period is accessed via the two 8-bit SFRs, PWMHI and PWMLOW.
PWM Generator // PWM #include
Chapter 12 # ) )* + Chapter 12 describes the ADC of the MSC1210. Topic Page 12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.4 Burnout Current Sources . . . . . . . . . . . . . . . .
Description 12.1 Description The MSC1210 includes an ADC with 24-bit resolution. The ADC consists of an input multiplexer (MUX), an optional buffer, a programmable gain amplifier (PGA), and a digital filter. The architecture is described diagram in Figure 12−1. Figure 12−1.
Input Multiplexer 12.2 Input Multiplexer The MSC1210 multiplexer is more flexible than a typical ADC in that each input pin can be configured as either a positive or negative input for a given measurement. While other ADC parts often define input pairs, the MSC1210 defines one pin as the negative input and the other as the positive input, thus providing complete design freedom in this respect.
Input Multiplexer The positive input channel and the negative input channel are selected in the ADC Multiplexer register (ADMUX, SFR D7h). The high four bits of ADMUX (bits 4 through 7) select the positive channel, while the low four bits (bits 0 through 3) select the negative channel. The ADMUX SFR has the following definition: SFR D7H 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01H INP3-0 (bits 7-4)—Input Multiplexer Positive Channel.
Temperature Sensor 12.3 Temperature Sensor As shown in the chart above describing the ADMUX SFR, when all bits are set to 1 (i.e. ADMUX = FFh), all the MUX inputs (AIN0-7, AINCOM) are disconnected from the ADC, and the ADC inputs are connected to measure two diode junctions with different currents. This differential voltage will change linearly with temperature, thus providing an integrated linear temperature sensor.
Temperature Sensor ADCON3 =(decimation>>8) & 0x07; // MSB of decimation ADCON1 = 0x01; // bipolar, auto, self calibration, offset, gain printf (”Calibrating. . .
Burnout Current Sources 12.4 Burnout Current Sources When the Burnout bit (BOD) is set in the ADC control register (ADCON0.6), two current sources are enabled that source approximately 2µA. This allows for the detection of an open circuit (full-scale reading) or short-circuit (0V differential reading) on the selected input differential pair. The following program illustrates a simple open-circuit and short-circuit detection routine. #include #include #include
Input Buffer The previous code detects either an open- or short-circuit situation based on the ADC sample. Also note that the comparison is less than 0.01, due to the fact that the ADC generally will not return exactly 0. 12.5 Input Buffer The input buffer reduces the likelihood of an offset in the measurements taken by the ADC. It should be used whenever the characteristics of the input signal allow.
Programmable Gain Amplifier (PGA) 12.7 Programmable Gain Amplifier (PGA) The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For example, with a PGA of 1 on a 5V full-scale range, the ADC can resolve to 1µV. With a PGA of 128 on a 40mV full-scale range, the ADC can resolve to 75nV. With a PGA of 1 on a 5V full-scale range, it would require a 26-bit ADC to resolve 76nV.
Offset DAC 12.8 Offset DAC The input to the PGA can be shifted by half the full-scale input range of the PGA by using the Offset DAC (ODAC) register (SFR address: 0xE6). The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the ODAC does not reduce the noise performance and increases the dynamic range of the ADC. The ODAC must be applied after any calibration is performed because the calibration will remove any offset induced by the ODAC.
Calibration 12.10 Calibration The offset and gain errors in the MSC1210 ADC, or a complete measurement system, can be reduced with calibration. The calibration mode control bits in the ADCON1 register (SFR address: 0xDD) can select 5 different calibration processes. These include: internal (self) calibration of offset, gain, or both, and system calibration of offset or gain. Each calibration process takes seven tDATA periods to complete.
Digital Filter 12.11 Digital Filter The digital filter can use either the fast settling, sinc2, or sinc3 filter, as shown in Figure 12−4. In addition, the auto mode changes the sinc filter to the best available option after the input channel or PGA is changed. When switching to a new channel, it will use the fast settling filter for the next two conversions, the first of which should be discarded. It will then use the sinc2 followed by the sinc3 filter to improve noise performance.
Digital Filter Figure 12−5.
Digital Filter 12.11.1 Multiplexing Channels When the input changes suddenly, it will take a certain amount of time for the output to correctly represent that new input. The amount of time required to correctly represent the new input depends on the type of filter being used. The filters are designed to settle in 1, 2 or 3 data output intervals. Up to an additional full period is required for an accurate sample because a change usually does not take place synchronous with the data output interval.
Voltage Reference Notice that the speed difference for the synchronized channel changes are only different by a factor of 3, whereas the non-synchronized channel has a factor difference of 4.5. These rates are all based on a reasonable speed for the modulation clock. In many applications, the mod clock can run as much as 10 times faster. That would make all of the times for throughput also 10 times faster, as shown in Table 12−5. Table 12−5.
Summation/Shifter Register 12.13 Summation/Shifter Register The MSC1210 includes a summation/shifter register that facilitates and increases the efficiency of certain common summation and shifting/division functions, especially those related to ADC conversions. The summation register is only active when the ADC is powered up. It is a 32-bit value that is broken into four 8-bit SFRs named SUMR0 (LSB), SUMR1, SUMR2, and SUMR3 (MSB).
Summation/Shifter Register SSCON1 and SSCON0 (SSCON.7 and SSCON.6, respectively) control which of the four modes the summation register will operate in. SCNT0, SCNT1, and SCNT2 (SSCON.3 through SSCON.5) are used to indicate how many ADC samples should be obtained and summed to the summation register.
Summation/Shifter Register 12.13.1 Manual Summation Mode The first mode of operation, manual summation, allows you to quickly add 32-bit values. In this mode, your program simply write the values to be added to the SUMR0, SUMR1, SUMR2, and SUMR3 SFRs. When a value is written to SUMR0, the current value of SUMR0-3 will be added to the summation register.
Summation/Shifter Register 12.13.3 Manual Shift (Divide) Mode The manual shift/divide mode provides a quick method of dividing the 32-bit number in the summation register by the value indicated by the SHF bits in SSCON. In assembly language terminology, this performs a 32-bit rotate right, dropping any bits shifted out of the least significant bit position.
Interrupt-Driven ADC Sampling 12.14 Interrupt-Driven ADC Sampling A useful, power-saving technique for obtaining ADC samples includes using the power-down mode of the MSC1210 between the time that a sample is requested and the time that a sample is made available to the MCU. During this time, the MSC1210 may be put into power-down mode by setting PCON.1 (PD). This will reduce power consumption significantly while the ADC sample is acquired.
Interrupt-Driven ADC Sampling ADCON2 = decimation & 0xFF; // LSB of decimation ADCON3 =(decimation>>8) & 0x07; // MSB of decimation ADCON1 = 0x01; // bipolar, auto, self calibration, offset, gain printf (”Calibrating. . .\n”); for (k=0; k<4; k++) { // Wait for Four conversions for filter to settle // after calibration. We go to sleep. When we wake // up, the interrupt will have read the sample.
Syncronizing Multiple MSC1210 Devices 12.15 Syncronizing Multiple MSC1210 Devices In some circumstances, it may be desirable to have data conversion synchronized between several devices. In order to synchronize the MSC1210, each of the devices will need to power down their ADCs (stop the clock), and then all devices restart their ADCs at the same time. For this explanation, we assume that one of the input port pins is defined to be the sync pin.
Syncronizing Multiple MSC1210 Devices #include #include #include #include #define LSB 298.0232e−9 /* LSB=5.
Ratiometric Measurements 12.16 Ratiometric Measurements Ratiometric measurements may be used to eliminate potential inaccuracy from the ADC process. Ratiometric measurements are obtained in a circuit similar to the one shown in Figure 12−6, where the same source used to drive the reference voltage (VREF) is used to drive the ADC (−IN).
Ratiometric Measurements 12.16.1 Differential VREF One application would be a system where the measurement and the ADC are on different grounds. Normally, you might have a voltage source that connects to a sensor, and the bottom of the sensor connects to the reference resistor. However, with two grounds, that can be different by more than 0.3V—that does not work. In such a case, you will need to connect the reference resistor from the power supply to the sensor, and then connect the sensor to GND2.
12-26
Chapter 13 $ , $ ! Chapter 13 describes the serial peripheral interface (SPI) of the MSC1210 ADC. Topic Page 13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4 SPI Signals . . . . . . . . . . . .
Description 13.1 Description The MSC1210 includes a serial peripheral interface (SPI) module that allows simple and efficient access to SPI-compatible devices via a number of SFRs provided for that purpose. The SPI is an independent serial communications subsystem that allows the MSC1210 to communicate synchronously with SPI peripheral devices and other microprocessors. The SPI is also capable of interprocessor communication in a multiple master system.
Functional Description Figure 13−2. SPI Clock/Data Timing During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave-select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities.
Clock Phase and Polarity Controls 13.3 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPICON 9AH). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two different transfer formats.
SPI Signals 13.4 SPI Signals The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS). The port register for P1.4, P1.5, P1.6 and P1.7 must be set (P1 = FxH) to use the SPI functions. Additionally, the pins must be setup as inputs or outputs using the Port 1 Data Direction register (P1DDRH, AFH). For master operation, P1DDRH = 75H (drive SS pin), and slave P1DDRH = DFH. 13.4.
SPI System Errors 13.5 SPI System Errors Some SPI systems define two types of system errors: write collision and mode fault. Write collision is defined to occur when a byte is written to the transmit register before the previous byte was sent. Mode fault is an error that occurs in multiple master systems when two masters try to write at the same time. There is no need to worry about write collision errors because the SPI transmit path is double-buffered.
Data Transfers 13.6 Data Transfers The transmitted and received data for SPI transfers are both double-buffered. This means that a second byte can be written for transmit before the first byte has been sent. Data that is received does not have to be read from the SPIDAT register until just before the next byte is received. The size of this buffer can essentially be extended with the FIFO mode. This adds from 2 to 128 bytes of FIFO memory.
Data Transfers The SPI Receive control register, SPIRCON (9CH), controls the data receive operation. The receive buffer can be flushed with the write only RXFLUSH bit. A flush operation changes the SPI receive pointer so that it points to the same address as the FIFO IN pointer, and clears the receive counter. The receive counter indicates the number of bytes that have been received. An interrupt can be generated when the receive count equals or exceeds a chosen number.
FIFO Operation 13.7 FIFO Operation Data transmitted by the SPI interface is written to the SPIDATA register. If the FIFO is enabled, it is stored in the FIFO memory. The first two bytes are immediately written to the transmit buffer, and the SPI transmit pointer is incremented. For each byte transmitted using the SCLK signal, a byte is also received. The received bytes are immediately transferred to the FIFO.
Code Examples 13.8 Code Examples 13.8.1 SPI Master Transfer in Double-Buffer Mode using Interrupt Polling Example 13−1. SPI Master Transfer in Double-Buffer Mode using Interrupt Polling 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 #include ”MSC1210.H” #include char spi_tx_rx ( char tx_data ) { while((AIE&0x08)!=0x08){ } SPIDATA=tx_data; // Wait until SPItx is set. while((AIE&0x04)!=0x04){ } return(SPIDATA); // Wait until SPIrx is set. } void main(void) { char j; P1DDRH = 0x75; // P1.7,P1.5,P1.
SPI Master Transfer in FIFO Mode using Interrupts 13.8.2 SPI Master Transfer in FIFO Mode using Interrupts Example 13−2. SPI Master Transfer in FIFO Mode using Interrupts 1 #include ”MSC1210.H” 2 void main(void) 3 { 4 P1DDRH = 0x75; // P1.7,P1.5,P1.4=output P1.
SPI Master Transfer in FIFO Mode using Interrupts Line 11 enables the SPIRX and SPITX interrupts, after which the AI flag is cleared and the EAI flag is enabled. There is no data to transmit, so SPITXIRQ goes up and we go to the monitor_isr() routine. The SPITX IRQ went up, so the subroutine send_4_bytes is called, where the program writes to the SPIDATA register 4 times. In line 20, the AI flag is cleared.
Chapter 14 # - % Chapter 14 describes addtional hardware on the MSC1210 ADC. Topic Page 14.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 14.1 Description The MSC1210 includes a number of special hardware features above and beyond those of a typical MCS−51 part. 14.2 Low-Voltage Detect The MSC1210 includes low voltage and brownout detection circuits for both the analog and digital supply voltages. The voltage levels at which these circuits are tripped is programmable. Figure 14−1.
Low-Voltage Detect The detect circuit must activate whenever the supply voltage drops below the programmed level. In order to account for temperature and process variations, the trip levels are typically higher than the specified value, to provide some margin. For example, when 4.5V is selected, the detect output will typically activate when the supply drops below 4.7V. 14.2.1 Power Supply VSPD powers the digital section resistor string and the comparators.
Watchdog Timer 14.3 Watchdog Timer The watchdog timer is used to ensure that the CPU is executing the user program and not some random sequence of instructions provoked by a malfunction. When the watchdog timer is enabled, the user program must periodically notify the watchdog that the program is still running correctly. If the watchdog detects that the user program has not made this notification after a certain amount of time, the watchdog automatically resets the MCS1210 or executes an interrupt.
Watchdog Timer Note: The HCR0 and HCR1 registers may be set by the TI downloader application at download time. It may also be set manually from within the source code by including the following assembly language code: CSEG AT 0807EH DB 0FCH ; Value for HCR0 DB 0FFH ; Value for HCR1 When the MSC1210 is in programming/download mode, code address 807EH refers to the HCR0 register and 807FH refers to the HCR1 register.
Watchdog Timer Although the watchdog timeout value (0x07 in the previous example) may be set at the same time as the EWDT bit is cleared, it may be changed after the fact. If the timeout value is changed after the watchdog has been enabled, the new timeout will take effect the next time the watchdog times out, or the next time the watchdog is reset (see next section).
Watchdog Timer 14.3.3 Resetting the Watchdog Timer Your program, when operating properly, must reset the watchdog periodically. You can reset the watchdog as frequently or infrequently as desired, as long as it is reset more frequently than the watchdog countdown time described previously. Your program must reset the watchdog by writing a 1 and then a 0 to the RWDT bit (WDTCON.5). This notifies the watchdog that your program is still operating correctly and that the watchdog timer should be reset.
Watchdog Timer 14.3.4 Disabling Watchdog Timer Once the watchdog timer is activated, it operates continuously and your program must reset the watchdog timer regularly, as described in the previous section. If, for some reason, you need to disable the watchdog timer (e.g., before entering idle mode), write a 1 and then a 0 to the DWDT (WDTCON.6) bit.
Chapter 15 # + Chapter 15 describes advanced topics associated with the MSC1210 ADC. Topic Page 15.1 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Advanced Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3 Breakpoint Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.4 Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Configuration 15.1 Hardware Configuration In addition to whatever amount of flash memory the specific MSC1210 part contains (which may be partitioned between flash data memory and flash program memory), the MSC1210 also includes 128 bytes of hardware configuration memory.
Hardware Configuration 15.1.1.1 Hardware Configuration Register 0 (HCR0) Hardware configuration register 0 (HCR0) is used to configure the amount of flash memory partitioned as data flash memory, configure the watchdog, and set a number of security bits that restrict write access to flash memory. The HCR0 has the following structure: CADDR 7FH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DSEL0 EPMA (bit 7)—Enable Program Memory Access (Security Bit).
Hardware Configuration 15.1.1.2 Hardware Configuration Register 1 (HCR1) Hardware configuration register 1 (HCR1) is used primarily to configure the brownout detection for both the digital and analog power supplies. It is also used to configure whether ports 0, 2, and 3 are used as general I/O ports, or take part in external memory access.
Hardware Configuration 15.1.2 Hardware Configuration Memory In addition to the hardware configuration registers, 116 bytes of configuration memory are available to you for your own use. This configuration memory, also set during device programming, can hold information such as unique serial numbers, parameters, or any other information that you want to record. The configuration information is available to the program when the part is operating for read operations, but cannot be changed.
Advanced Flash Memory 15.2 Advanced Flash Memory Flash memory may be configured as data memory, program memory, or both. 15.2.1 Write Protecting Flash Program Memory Flash program memory may be protected against your program overwriting it by writing to flash memory during program execution. This provides a safeguard to the integrity of the code against intentional or accidental manipulation by your program.
Breakpoint Generator 15.3 Breakpoint Generator The purpose of the breakpoint block is to generate an interrupt whenever the desired program or data memory address is accessed. There are two kinds of memory accesses it can detect: - Accesses to program memory (read or write) - Accesses to data memory (read or write) The interrupt is handled by the interrupt controller (for details, see Chapter 10, Interrupts). Breakpoints are useful in debugging code.
Breakpoint Generator To configure a breakpoint, the following steps should be taken: 1) The BPSEL (MCON.7) bit must be set to either 0 (for Breakpoint 0) or 1 (for Breakpoint 1). 2) The Program Memory Select bit, PMSEL (BPCON.1), must be either cleared if the breakpoint is to detect an access to data memory, or set if the breakpoint is to detect an access to program memory. 3) BPL and BPH should be loaded with the low and high byte, respectively, of the address at which the breakpoint should be triggered.
Power Optimization 15.4 Power Optimization The MSC1210, like a standard 8052, has the ability to operate in a power-saving mode, known as idle mode. As the name implies, idle mode shuts down most of the energy-consuming functions of the microcontroller and idles. Code execution stops in idle mode, and the only way to exit idle mode is a system reset or an enabled interrupt being triggered. Idle mode is useful in causing the microcontroller to go to sleep until an interrupt awakens it.
Flash Memory as Data Memory 15.5 Flash Memory as Data Memory If so configured in HCR0, some portion of flash memory can be accessed by your application program as flash data memory. The amount of flash memory that is partitioned as flash data memory is controlled by the low 3 bits of HCR0. Please see Section 15.1.1.1, Hardware Configuration Register 0, for details.
Flash Memory as Data Memory unsigned char i; // synchronize baud rate autobaud(); // Set the pointer to the beginning of the page to modify pFlashPage = (char xdata * ) PAGE_START; // before writing the flash, we have to initialize // the usec and msec SFRs because the flash programming // routines rely on these SFRs USEC = 12−1; // assume a 12 MHz clock MSEC = 12000−1; while(1) { // copy the page from FLASH to RAM for(i=0;i
Advanced Topics and Other Information 15.6 Advanced Topics and Other Information 15.6.1 Serial and Parallel Programming of the MSC1210 The MSC1210 flash program memory may be updated either in a serial or parallel fashion. In these cases, the process is controlled by protocol that allows the PC (or other external device) and the MSC1210 to communicate. This protocol is described in http://www−s.ti.com/sc/psheets/sbaa076a/sbaa076a.pdf. 15.6.
Chapter 16 . / 0# 01 Chapter 16 describes the 8052 Assembly Language. Topic Page 16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3 Number Bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4 Expressions . .
Description 16.1 Description Assembly language is a low-level, pseudo-English representation of the microcontroller’s machine language. Each assembly language instruction has a one-to-one relation to one of the microcontroller machine-level instructions. High-level languages, such as C, Basic, Visual Basic, etc. are one or more steps above assembly language, in that no significant knowledge of the underlying architecture is necessary.
Syntax In summary, a typical 8052 assembly language line might appear as: MYLABEL: MOV A,#25h ;This is just a sample comment In this line, the label is MYLABEL. This means that if subsequent instructions in the program need to make reference to this instruction, they may do so by referring to MYLABEL, rather than the memory address of the instruction. The 8052 assembly language instruction in this line is MOV A,#25h.
Number Bases 16.3 Number Bases Most assemblers are capable of accepting numeric data in a variety of number bases. Commonly supported are decimal, hexadecimal, binary, and octal. Decimal: To express a decimal number in assembly language, simply enter the number normally. Hexadecimal: To express a hexadecimal number, enter the number as a hexadecimal value, and terminate the number with the suffix “h”. For example, the hexadecimal number 45 is expressed as 45h.
Operator Precedence 16.5 Operator Precedence Mathematical operators within an expression are subject to the following order of precedence. Operators at the same “level” are evaluated left to right. Table 16−1.
Changing Program Flow (LJMP, SJMP, AJMP) 16.7 Changing Program Flow (LJMP, SJMP, AJMP) LJMP, SJMP and AJMP are used as a go to in assembly language. They cause program execution to continue at the address or label they specify.
Subroutines (LCALL, ACALL, RET) 16.8 Subroutines (LCALL, ACALL, RET) As in other languages, 8052 assembly language permits the use of subroutines. A subroutine is a section of code that is called by a program, does a task, and then returns to the instruction immediately following that of the instruction that made the call. LCALL and ACALL are both used to call a subroutine. LCALL requires three bytes of program memory and can call any subroutine anywhere in memory.
Register Assignment (MOV) Note: Recursive subroutines (subroutines that call themselves) are a very popular method of solving some common programming problems. However, unless you know for certain that the subroutine will call itself a certain number of times, it is generally not possible to use subroutine recursion in 8052 assembly language. Due to the small amount of Internal RAM a recursive subroutine could quickly cause the stack to fill all of internal RAM. 16.
Register Assignment (MOV) As already mentioned, the MOV instruction is one of the most common and vital instructions that an 8052 assembly language programmer uses. The prospective assembly language programmer must fully master the MOV instruction. This may seem simple, but it requires knowing all of the permutations of the MOV instruction and knowing when to use them. This knowledge comes with time and experience, and by reviewing Appendix A, 8052 Instruction Set Overview.
Register Assignment (MOV) With this knowledge of the MOV instruction, some simple memory assignment tasks can be performed: 1) Clear the contents of Internal RAM address FFH: MOV A,#00h ;Move the value 00h to the accumulator ;(accumulator=00h) MOV R0,#0FFh ;Move the value FFh to R0 (R0=0FFh) MOV @R0,A ;Move accumulator to @R0, thus clearing ;contents of FFh 2) Clear the contents of Internal RAM address FFH (more efficient): MOV R0,#0FFh ;Move the value FFh to R0 (R0=0FFh) MOV @R0,#00h ;Move 00h to @R0
Incrementing and Decrementing Registers (INC, DEC) 16.10 Incrementing and Decrementing Registers (INC, DEC) Two instructions, INC and DEC, can be used to increment or decrement the value of a register, internal RAM, or SFR by 1. These instructions are rather self-explanatory. The INC instruction will add 1 to the current value of the specified register. If the current value is 255, it will overflow back to 0.
Program Loops (DJNZ) 16.11 Program Loops (DJNZ) Many operations are conducted within finite loops. That is, a given code segment is executed repeatedly until a given condition is met. A common type of loop is a simple counter loop. This is a code segment that is executed a certain number of times and then finishes. This is accomplished easily in 8052 assembly language with the DJNZ instruction. DJNZ means decrement, jump if not zero.
Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV) 16.12 Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV) One very powerful feature of the 8052 architecture is its ability to manipulate individual bits on a bit-by-bit basis. As mentioned earlier in this document, there are 128 numbered bits (00H through 7FH) that may be used by the user’s program as bit variables. Additionally, bits 80H through FFH allow access to SFRs that are divisible by 8 on a bit-by-bit basis.
Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV) Finally, the SETB TR1 example shows a typical use of SETB to set an individual bit of an SFR. In this case, TR1 is TCON.6 (bit 6 of TCON SFR, SFR address 88H). Due to TCON’s SFR address being 88H, it is divisible by 8 and, thus, addressable on a bit-by-bit basis. The CLR instruction functions in the same manner, but clears the specified bit. For example: CLR 20h ;Clears user bit 20h to 0 CLR P0.
Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC) 16.13 Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC) It is often useful, especially in microcontroller applications, to execute different code based on whether or not a given bit is set or cleared. The 8052 instruction set offers five instructions that do precisely that. JB means jump if bit set. The MCU checks the specified bit and, if it is set, jumps to the specified address or label. JBC means jump if bit set, and clear bit.
Value Comparison (CJNE) 16.14 Value Comparison (CJNE) CJNE (compare, jump if not equal) is a very important instruction. It is used to compare the value of a register to another value and branch to a label based on whether or not the values are the same. This is a very common way of building a switch…case decision structure or an IF…THEN…ELSE structure in assembly language.
Less Than and Greater Than Comparison (CJNE) Code structures similar to the one shown previously are very common in 8052 assembly language programs to execute certain code or subroutines based on the value of some register, in this case the accumulator. 16.15 Less Than and Greater Than Comparison (CJNE) Often it is necessary not to check whether a register is or is not certain value, but rather to determine whether a register is greater than or less than another register or value.
Zero and Non-Zero Decisions (JZ/JNZ) 16.16 Zero and Non-Zero Decisions (JZ/JNZ) Sometimes, it is useful to be able to simply determine if the accumulator holds a zero or not. This could be done with a CJNE instruction, but because these types of tests are so common in software, the 8052 instruction set provides two instructions for this purpose: JZ and JNZ. JZ will jump to the given address or label if the accumulator is zero. The instruction means jump if zero.
Performing Additions (ADD, ADDC) This code assumes that a 16-bit number is in Internal RAM address 30H (high byte) and address 31H (low byte). The code will add 1045H to the number, leaving the result in addresses 32H (high byte) and 33H (low byte).
Performing Subtractions (SUBB) 16.18 Performing Subtractions (SUBB) The SUBB instruction provides a way to perform 8-bit subtraction. All subtraction involves subtracting some number or register from the accumulator and leaving the result in the accumulator. The original value in the accumulator is always overwritten with the result of the subtraction.
Performing Multiplication (MUL) 16.19 Performing Multiplication (MUL) In addition to addition and subtraction, the 8052 also offers the MUL AB instruction to multiply two 8-bit values. Unlike addition and subtraction, the MUL AB instruction always multiplies the contents of the accumulator by the contents of the B register (SFR F0H). The result overwrites both the accumulator and B, placing the low byte of the result in the accumulator and the high byte of the result in B.
Performing Division (DIV) 16.20 Performing Division (DIV) The last of the basic mathematics functions offered by the 8052 is the DIV AB instruction. This instruction, as the name implies, divides the accumulator by the value held in the B register. Like the MUL instruction, this instruction always uses the accumulator and B registers. The integer (whole-number) portion of the answer is placed in the accumulator and any remainder is placed in the B register.
Shifting Bits (RR, RRC, RL, RLC) 16.21 Shifting Bits (RR, RRC, RL, RLC) The 8052 offers four instructions that are used to shift the bits in the accumulator to the left or right by one bit: RR A, RRC A, RL A, RLC A. There are two instructions that shift bits to the right, RR A and RRC A, and two that shift bits to the left, RL A and RLC A. The RRC and RLC instructions are different in that they rotate bits through the carry bit, whereas RR and RL do not involve the carry bit.
Bit-Wise Logical Instructions (ANL, ORL, XRL) 16.22 Bit-Wise Logical Instructions (ANL, ORL, XRL) The 8052 instruction set offers three instructions to perform the three most common types of bit-level logic: logical AND (ANL), logical OR (ORL), and logical exclusive OR (XRL). These instructions are capable of operating on the accumulator or an internal RAM address.
Bit-Wise Logical Instructions (ANL, ORL, XRL) Most of the logical bit-wise instructions affect entire 8-bit memory registers. However, the following instructions are available to perform logical operations on the carry bit. The result of these instructions is always left in the carry bit and the other bit is left unchanged. ANL C,bit—this instruction will perform a logical AND between the carry bit and the specified bit. If both bits are set, the carry bit remains set. Otherwise, the carry bit is cleared.
Exchanging Register Values (XCH) 16.23 Exchanging Register Values (XCH) Very often, the value of the accumulator will need to be swapped with the value of another SFR or internal RAM address. The XCH instruction allows this to be done quickly and without using additional temporary holding variables. XCH will take the value of the accumulator and write it to the specified SFR or internal RAM address, while at the same time writing the original value of that SFR or internal RAM address to the accumulator.
Adjusting Accumulator for BCD Addition (DA) 16.26 Adjusting Accumulator for BCD Addition (DA) DA A is a very useful instruction if you are doing BCD-encoded addition. BCD stands for binary coded decimal, and is a form of expressing two decimal digits in a single 8-bit byte. When any 8-bit value is expressed in hexadecimal, it can be expressed as a number between 00 and FF.
Using the Stack (PUSH/POP) 16.27 Using the Stack (PUSH/POP) The stack, as with any processor, is an area of memory that can be used to store information temporarily, including the return address for returning from subroutines that are called by ACALL or LCALL. The 8052 automatically handles the stack when making an ACALL or LCALL, as well as when returning with the RET instruction.
Using the Stack (PUSH/POP) The stack itself resides in internal RAM and is managed by the SP (stack pointer) SFR. SP will always point to the internal RAM address from which the next POP instruction should obtain the data. - POP will return the value of the internal RAM address pointed to by SP, then decrement SP by 1. - PUSH will increment SP by 1, then store the value at the IRAM address then pointed to by SP. SP is initialized to 07H when an 8052 is first powered up.
Setting the Data Pointer DPTR (MOV DPTR) 16.28 Setting the Data Pointer DPTR (MOV DPTR) The next few instructions use the data pointer (DPTR), the only 16-bit register in the 8052. DPTR is used to point to a RAM or ROM address when used with the following instructions that are explained. As described earlier, DPTR is really made up of two SFRs: DPH and DPL which hold the high and low bytes, respectively, of the 16-bit data pointer.
Reading and Writing External RAM/Data Memory (MOVX) 16.29 Reading and Writing External RAM/Data Memory (MOVX) The 8052 generally has 128 or 256 bytes of internal RAM that is accessed with the MOV instruction, as described previously. However, many projects will require more than 256 bytes of RAM. The 8052 has the ability of addressing up to 64k of external RAM in the form of additional, off-chip ICs. The MOVX instruction is used to read from and write to external RAM.
Reading Code Memory/Tables (MOVC) 16.30 Reading Code Memory/Tables (MOVC) It is often useful to be able to read code memory itself from within a program. This allows for the placement of data or tables in code memory to be read at run time by the program itself. This is accomplished by the MOVC instruction. The MOVC instruction comes in two forms: MOVC A,@A+DPTR and MOV A,@A+PC. Both instructions move a byte of code memory into the accumulator.
Reading Code Memory/Tables (MOVC) For example, if the data in the previous example are located right after the routine that read it, instead of being located at code memory 2000H, the subroutine could be changed to: SUB: INC A ;Increment accumulator to account for ;RET instruction MOVC A,@A+PC ;Get the data from the table RET ;Return from subroutine DB 01h,02h,03h,04h,05h ;The actual data table Note: In the above example, we first increment the accumulator by 1.
Using Jump Tables (JMP @A+DPTR) 16.31 Using Jump Tables (JMP @A+DPTR) A frequent method for quickly branching to many different areas in a program is by using jump tables.
Chapter 17 2 Chapter 17 describes the Keil simulator and its functions. Topic Page 17.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.4 Watchdog Timer . . . . . . . . . . .
Description 17.1 Description The µVision2 is an integrated software development platform that combines a robust screen editor, and project manager with make facilities. In addition, the Keil package has an integrated source-level debugger that contains a high-speed simulator that gives you the ability to simulate the entire 8051 system. This includes the full complement of the 8051 resources, and the MSC1210 specific onchip peripherals and external hardware peripherals.
Description 3) There are also some labeled check boxes whose statuses, checked or cleared, directly affect the associated bit within the respective bit pattern of the SFR. A checked status on a check box item represents a logic 1, while a cleared status on a check box item represents a logic 0. Conversely, the current status of the corresponding bit within the associated bit pattern of the SFR is reflected in the pertinent check box.
Timers 17.2 Timers The simulator peripheral timer has three timer/counter modules: Timers 0, 1, and 2; a system timer module; and a watchdog module. The Timer/Counter 0 module is identical to the Timer/Counter 1, so we shall only describe the operations of Timer/Counter 0. Figure 17−1. Timer/Counter 0 − Mode 2 The first of the two selection boxes provides a list of four timer-operating modes upon activation, from which you are allowed to choose.
Timers Due to the MSC1210 peripherals being modular and relatively independent, even if they share registers, each peripheral has it own unique set of bits that are associated and affiliated with it. For instance, referring to the Chapter 8, Timers, the status and setup bits for both Timer/Counter 0 and Timer/Counter 1 occupy separate bit positions within the same TCON SFR. The same holds for the TMOD register. 17.2.
Timers Figure 17−4. Timer/Counter 1 Mode 1 Figure 17−5.
Timers The following is a listing of the C code used to demonstrate the timing and interrupting features of Timer/Counters 0 and 1. The included statements on the first three lines are the conventional ANSI C include statements for adding the contents of different header files to a C program. There are four routines including the main ( ) program that are needed to run this program. They are described in the following paragraphs. #include ”MSC1210.h” #include #include
Timers void interrupt_timer0 ( ) interrupt 1 using 1 { /*This ISR is called when a type 1 interrupt causes the processor to vector into the code segment address 0x0006. Register Bank 1 is used, as opposed to the default Register Bank 0.
Timers Every time the idle loop is interrupted, the MSC1210 vectors to the ISR of the interrupting signal. If the interrupt source is the Timer 0 overflow, the processor vectors to the interrupt_timer 0 ( ) ISR, where the timer_0_overflow_count variable is updated, and the TH0:TL0 register pair is replenished with a value of 0x0200. If the external Interrupt 0 signal is the interrupt source, the interrupt_external 0 ( ) is vectored to. This ISR keeps track of even and odd ISR calls.
Timers end_test = 0; //Timer 0 TH0:TL0 will always count up from 0x0200 until overflow, //and will be replenished with 0x0200 indefinitely count_start = 0x200; /*Timer 0 and Timer 1 in Mode 1, timer mode, Gate 0 is closed and Gate 1 is opened.
Timer 2 17.3 Timer 2 Timer/Counter 2 is quite different from the two other timers. The operation mode is determined by the status of one or more of the register bits displayed in Table 17−1. Table 17−1.Timer/Counter 2 Control Bits Register Bit Toggle Box Name T2CON.TR2 TR2 T2CON.C/T2 TC/T T2CON.CP/RL2 CP/RL2 T2CON.EXEN2 EXEN2 T2CON.TCLK TCLK T2CON.RCLK RCLK Figure 17−6.
Watchdog Timer 17.4 Watchdog Timer The process of setting, and the operation of the watchdog timer peripheral facility are similar to those of the other peripherals we have considered so far. However, this module has an additional feature: the special access setting or resetting of the status conditions of the EWDT, DWDT, RWDT check boxes. These boxes directly or indirectly affect, or are affected by, the status and conditions of the EWDT, DWDT, RWDT bits of the WDTCON SFR respectively.
Watchdog Timer The non-editable Expire in: display window indicates the amount of time left (in milliseconds) before you must perform either a timed access watchdog reset or a watchdog disable, in order to avoid the watchdog timer initiating a system reset (if watchdog reset is enabled). Note that PDWDT does not enable the watchdog timer reset; it is enabled and disabled by the WDRESET bit in hardware configuration register 0 (HCR0).
Watchdog Timer /* //For the actual device, the a logical AND of the content of the FRC0 SFR register with 0xF7 must be performed to Disable the Watchdog Reset so that the watchdog system can be controlled through the watchdog interrupt facility.
Watchdog Timer /*start short loop to test DWDT*/ for (i = 0; i < 4000; i ++) {//idle delay j = (i *13) % 4000; } //Disable watchdog timer before timer expires WDTIMER |= 0x40; WDTIMER &= ~0x40; //Reinitialize watchdog, sinice it has just been disabled init_watchdog ( ); /*start short loop to test RWDT*/ for (i = 0; i < 400; i ++) {//idle delay j = (i *13) % 4000; } /*Reset Watchdog Timer before Watchdog Timer Expires*/ WDTIMER |= 0x20; WDTIMER &= ~0x20; /*Infinite loop to test Watchdog Timer Time out with i
System Timer 17.5 System Timer The MSC1210 device has many time ticks and an additional clock generator (1MHz) that are derived, and, therefore, synchronized to the system clock. Each time tick and clock generator has a set of registers that specify the value of system clock divisions required to generate it. Some of these registers are accessible through the system timer peripheral windows. The editable XTAL Freq.: window allows you to set the crystal clock frequency.
Analog-to-Digital Converter 17.7 Analog-to-Digital Converter Data entry and bit pattern setting facilities for the ADC peripheral are similar to those of the other peripherals. Some of the text entry boxes are editable, while others are just read-only, and the check boxes respond to mouse clicks with checked and cleared status. The editable text entry windows marked ADCON0, ADCON1, ADCON2 and ADCON3 provide direct access to the ADC Control registers 0, 1, 2 and 3, respectively.
Analog-to-Digital Converter Figure 17−8. Analog−to−Digital Converter Peripheral For each analog input source whose editable text windows are displayed under the Analog Input Channels title, one could specify the desired analog voltages to be converted. The µVision2 simulator also provides an alternate way for entering analog voltage values by writing a script program that runs in parallel with the program being executed. A sample code is appended.
Analog-to-Digital Converter SIGNAL void a_to_d_sim (void) { inti; /*Data written into the variable ain0 is automatically entered into the editable text window labeled AIN0 in the ADC peripheral dialog.*/ ain0 = 0.5; //specify start value for ain0 //debug program idles for 196000 clock cycles, while simulation continues running in parallel*/ twatch (196000); /*the following loop sends out 64 consecutive samples of ain0,each incremented by 0.01.
Summation/Shifter 17.8 Summation/Shifter The summation/shifter module implemented in this simulator package allows the developer to experience how the automatic data averaging works. It also allows the program to be tested while it is being developed. Figure 17−10 shows a snapshot of the summation/shifter peripheral in the middle of a data acquisition cycle.
Summation/Shifter The non-editable text window across from the acc count shows the current number of data samples accumulated into the summation registers for the current accumulate & shift cycle. The summation/shifter module depicted in Figure 17−10 shows that five samples had been accumulated, and the concatenated result of the summation registers for the freeze−framed accumulate & shift cycle, up to that point, was 0x00AE1479.
Summation/Shifter This setting essentially causes the 32-bit accumulator to collect eight consecutive data samples from the ADC. Upon completion, it divides the result by eight, by implementing a 3-bit position arithmetic right shift. In other words, it computes the average value of eight consecutive samples. The following is the C code for the sample exercise described above: #include ”MSC1210.
Summation/Shifter to a LONG integer*/ long j; j = ACR3; j <<= 8; j += ACR2; j <<= 8; j += ACR1; j <<= 8; j += ACR0; return (j); } long read_a_to_d_result () { long j; /*Convert A/D Conversion results from the ADRESH:ADRESM:ADRESL register string to a LONG integer ith sign extension*/ j = ADRESH; j <<= 8; j += ADRESM; j <<= 8; j += ADRESL; j &= 0x00ffffff; //eleminate upper nibble if (j & 0x00800000) {//is result negative? j |= 0x0ff000000; } return (j); } char init_a_to_d () { char i, j; /* Setup ADC */ //
Summation/Shifter while(!(AISTAT & 0x20)); j = ADRESL; for (i = 0; i < 20; i++) { // dump 20 conversions /*wait for DRBY bit*/ while(!(AISTAT & 0x20)); } /*set up Summation / Shifter*/ /*Select Summation / Shifter option, Acc Count = 8, Shift Count = 8 */ init_accumulator (); //extract Accumulate−Count from SSCON SFR Register. j = SSCON & 0x38; j /= 8; j = 1 << (j + 1); return (j); } void a_to_d_accumulate (void) interrupt 6 using 1 { /*interrupt type 6 vectored to 0x33.
Summation/Shifter char accum_count; long l; float voltage_value, vref, max_range; char convert_accumulate; convert_accumulate = 1; //Select data averaging option.
Summation/Shifter } switch (convert_accumulate) { case CONVERT: //straight A/D conversion results, no averaging PAI = 0x20; for (i = 0; i < 0x40; i++) { converting = 1; /*straight conversion idle loop. Value of ”converting” is changed in the a_to_d_accumulate () ISR which is called at the end of each conversion.
Summation/Shifter In order to demonstrate how the summation/shifter handles the incremental accumulation of sampled data, we have opted to enable both the ADC conversion interrupt enable, EADC, and the summation interrupt enable, ESUM, by assigning a value of 0x60 to the PIREG SFR. This implies that the power fail interrupt, AI, is pulsed each time the ADC completes a sample conversion on ADC, and each time the number of accumulation matches the acc_count value on SUM.
Summation/Shifter Figure 17−11. summation/Shifter Peripheral Figure 17−12.
Summation/Shifter In addition to the previous sample code, a sample driving code for the debugging is included below. This is a special feature of the µVision2 Simulator system that allows you to send input voltage values to the editable analog text fields in the ADC peripheral module. In the case of this example, the AIN0 input channel is selected.
Interrupts 17.9 Interrupts The list box for the interrupt peripheral is shown in Figure 17−13. The figure shows a list of interrupt sources along with their associated vector addresses that the processor automatically vectors to in the event that an enabled interrupt is triggered, there are no pending interrupt requests of higher priority, and there is no ISR being executed pertaining to an interrupt source of higher priority.
Ports 17.10 Ports There are four parallel I/O ports on this device, Port 0, Port 1, Port 2 and Port 3, and as such, there are four separate parallel port displays. We shall discuss the operation of just one I/O port display because all four of them are similar. The Parallel Port 0 shown in Figure 17−14 depicts the value and the bit pattern of the contents on the Port 0 register (P0), the Port 0 Data Direction High register P0DDRH, and the Port 0 Data Direction Low register P0DDRL.
Serial Peripheral Interface (SPI) 17.11 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) implemented in this simulator package mimics the behavior and characteristics of a data memory access (DMA) SPI module, integrated into the MSC1210. The MSC1210 SPI module is an enhanced version of the popular SPI modules implemented by other manufacturers.
Serial Peripheral Interface (SPI) data displayed in the SPICON window, on the basis of the bit position of the corresponding configuration bit within the SFR bit pattern. Likewise, changing the clock rate divide by value changes the SPICON entry accordingly. The result of the oscillator frequency divided by the selected divide by factor is displayed in the non-editable master clock window.
Serial Peripheral Interface (SPI) and the TXIRQ window determine the check/clear status of the SPIT check box. As data is being received from the external device, the value of the received data will be momentarily displayed in the SPIDATA window, and the content of SPIRCON window is properly updated. In addition, as data is read from the circular buffer, the value displayed in the SPIEND windows is properly updated.
Serial Peripheral Interface (SPI) #include ”MSC1210.
Serial Peripheral Interface (SPI) SPIEND = 0x0b0; /*Master mode: set MISO for input, and MOSI, SS & SCK for strong outputs*/ P1DDRH = 0x75; P1 |= 0xF0; /*enable SPI interrupt*/ PIREG |= 0x0c; IE |= 0x80; EPFI = 1; } void transmit_receive () interrupt 6 using 1 { /*This is a type 6 interrupt (AI). Processor vectors to 0x33, from which it is redirected to this ISR.
Serial Peripheral Interface (SPI) if (AISTAT & 0x04) {/*Receiver*/ i = SPIRCON & 0x7F; //extract the count for the number of AISTAT &= ~0x04; //deactivate SPI receive flag if (l >= 50) { /*do not exceed the 50 received_data[] array limit*/ for (l = 0; l < 5; l++) { printf (”\n”); for (k = 0; k < 10; k++) { printf (” %c”, received_data[k + l * 10] ); } } printf (”\n”); l=0; //reset the received_data[] array index.
mVision 2 Debug Program Example 17.12 µVision 2 Debug Program Example SIGNAL void spi_sim (void) { /*This program runs in parallel with the main program. It sends out a character byte whose value is post incremented at the end of each associated time lapse. SPI_IN is the portal through which the byte data is sent to the main program.
mVision 2 Debug Program Example Figure 17−17. Keil Debugger The window labeled Serial #1 shows the printed ASCII character representation of the data bytes received by the main SPI program from the debugging program. Note that the first character printer is an ! mark which has a numerical value of 0x21. This was the first value of j to be transmitted from the debugger through the SPI_IN portal.
Serial Port I/O 17.13 Serial Port I/O In addition to the SPI communication protocol that was presented earlier in this manual, the more basic serial port I/O was also implemented in this simulator. Serial Ports 0 and 1 are simulated in this package. An example of this communication protocol has been used a couple of times in this section of the manual. The show_baud_gen ( ) subroutine is used to set up the output display of programming example results on the Serial #1 window.
Serial Port I/O A snapshot of the Serial Channel 0 communication peripheral after at typical show_baud_gen ( ) subroutines execution is shown in Figure 17−18. Figure 17−18. Serial Channel 0 Communication Peripheral The statuses of the transmit and/or receive flags are also reflected in the conditions of the TI_0 and RI_0 check boxes. The computed transmit and receive baudrates are displayed in the transmit baud rate and the receive baud rate non-editable windows respectively.
Serial Port I/O 17.13.1 Serial Port 0 Operation Mode 1 Example void show_baud_gen (void) { P3DDRL &= 0xf0; P3DDRL |= 0x07; //P30 input, P31 output TF2 = CLEAR; T2 = CLEAR; CKCON |= 0x30; // Set timer 2 to clk/4 RCAP2 = 0xFF16; //37500 bps THL2=0xFFFF; /* Set T2 for Serial0 Tx baudgen. Timer 2 is designated the clock source for the ”divide by 16” clock for the Transmit block, while Timer 1 is the implied source for the ”divide by 16” clock for the Receive block.
Serial Port I/O 17.13.2 Transmit Block Baud Rate Computation In this example, two different baud rate sources have been used, one for receive, Timer 1 overflow, and the other for transmit, Timer 2 overflow. Of course, there is no good reason for this, except to show that it could be done, and to show how to use different timer modes for baud rate generation. The analyses for operational parameters for the individual timer overflow sources are described in the following paragraphs.
Serial Port I/O 17.13.3 Receive Block Baud Rate Computation Timer 1 is set for a mode 2 timer operation in an 8-bit auto-reload capacity. This is achieved by assigning a 0x20 value to the TMOD SFR. Recall that the SMOD0 bit of PCON has been set in an earlier section of this program. This effectively doubles the communication baud rate.
Serial Port I/O Figure 17−19. Clock Control Peripheral Figure 17−20.
Additional Resource 17.14 Additional Resource It is highly recommended that you review the Keil Compiler tutorial integrated into this package for an animated demonstration of some useful IDE facilities.
Appendix A # 0 0 0 0 0 0 0. / Appendix A deals with additional features found in the MSC1210 as compared to the 8052. Topic A.1 Page Addtional Features in the MSC1210 Compared to the 8052 . . . . . . .
Additional Features in the MSC1210 Compared to 8052 A.1 Additional Features in the MSC1210 Compared to 8052 The MSC1210 includes the following features in addition to those that are included in a standard 8052 microcontroller. - Flash memory, up to 32k partitionable as program and/or data memory. - Low-voltage/brownout detection. - High-speed core: 4 clocks per instruction cycle. - Dual data pointers (DPTR).
Appendix B 30 0* Appendix B diagrams the MSC1210 ADC timing chain and clock control. Topic B.1 Page MSC1210 Timing Chain and Clock Control Diagram . . . . . . . . . . . . . .
MSC1210 Timing Chain and Clock Control Diagram B.1 MSC1210 Timing Chain and Clock Control Diagram Figure B−1.
Appendix C " 0 0 Appendix C defines the MSC1210 ADC boot ROM routines. Topic C.1 Page Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description C.1 Description The MSC1210 has a 2K ROM. This code provides the interaction for serial and parallel programming. There are also several routines that are useful and necessary for use with user applications. For example, when writing to flash memory, the code cannot execute out of flash memory. By calling the flash write routine in ROM, this condition is satisfied. Convenient access to those routines is supplied through a jump table summarized in Table C−1. Table C−1.
Description C parameters are passed to the subroutine code such that the first parameter is passed in R7, whereas additional parameters use lower R registers (R7 first, then R6, R5, etc.). In the case of multibyte parameters, the low byte uses the next available R register while the high byte uses the lower R register. Thus, the put_string routine uses R7 to receive the low byte of the address of the string while R6 is used to receive the high byte of the address of the string.
C-4
Appendix D . / 0 ) 04 3) , 0( Appendix D gives a list of the 8052 instruction set. Topic D.1 Page 8052 Instruction-Set Quick-Reference Guide . . . . . . . . . . . . . . . . . . . .
8052 Instruction-Set Quick-Reference Guide D.
Appendix E . / 0 0 Appendix E lists the 8052 instruction set. Topic Page E.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 E.2 8052 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description E.1 Description This appendix is a reference for all instructions in the 8052 instruction set. For each instruction, the following information is provided: - Instruction—indicates the correct syntax for the given opcode. - OpCode—the operation code, in the range of 0x00 through 0xFF, that rep- resents the given instruction in machine code. - Bytes—the total number of bytes (including the opcode byte) that make up the instruction.
8052 Instruction Set E.2 8052 Instruction Set ACALL Absolute Call within 2k Block Syntax ACALL codeAddress Instructions ACALL pg0Addr OpCode 0x11 Bytes 2 Cycles 2 Flags None ACALL pg1Addr ACALL pg2Addr ACALL pg3Addr ACALL pg4Addr ACALL pg5Addr ACALL pg6Addr ACALL pg7Addr 0x31 0x51 0x71 0x91 0xB1 0xD1 0xF1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 None None None None None None None ACALL unconditionally calls a subroutine at the indicated code address.
8052 Instruction Set ADD, ADDC Add Value, Add Value with Carry Syntax ADD A,operand ADDC A,operand Instructions OpCode Bytes Cycles Flags ADD A,#data8 0x24 2 1 C, AC, OV ADD A,direct 0x25 2 1 C, AC, OV ADD A,@R0 0x26 1 1 C, AC, OV ADD A,@R1 0x27 1 1 C, AC, OV ADD A,R0 0x28 1 1 C, AC, OV ADD A,R1 0x29 1 1 C, AC, OV ADD A,R2 0x2A 1 1 C, AC, OV ADD A,R3 0x2B 1 1 C, AC, OV ADD A,R4 0x2C 1 1 C, AC, OV ADD A,R5 0x2D 1 1 C, AC, OV ADD A,R6 0x2E 1 1 C,
8052 Instruction Set The auxillary carry (AC) bit is set if there is a carry-out of bit 3. In other words, if the unsigned summed value of the low nibble of the accumulator, operand, and (in the case of ADDC) the carry flag exceeds 15, the auxillary carry flag is set. Otherwise, the auxillary carry flag is cleared. The overflow (OV) bit is set if there is a carry-out of bit 6 or out of bit 7, but not both.
8052 Instruction Set ANL Bitwise AND Syntax ANL operand1,operand2 Instructions OpCode Bytes Cycles Flags ANL direct,A 0x52 2 1 None ANL direct,#data8 0x53 3 2 None ANL A,#data8 0x54 2 1 None ANL A,direct 0x55 2 1 None ANL A,@R0 0x56 1 1 None ANL A,@R1 0x57 1 1 None ANL A,R0 0x58 1 1 None ANL A,R1 0x59 1 1 None ANL A,R2 0x5A 1 1 None ANL A,R3 0x5B 1 1 None ANL A,R4 0x5C 1 1 None ANL A,R5 0x5D 1 1 None ANL A,R6 0x5E 1 1 None ANL A,R7 0
8052 Instruction Set CJNE Compare and Jump if Not Equal Syntax CJNE operand1,operand2,reladdr Instructions OpCode Bytes Cycles Flags CJNE A,#data8,reladdr 0xB4 3 2 C CJNE A,direct,reladdr 0xB5 3 2 C CJNE @R0,#data8,reladdr 0xB6 3 2 C CJNE @R1,#data8,reladdr 0xB7 3 2 C CJNE R0,#data8,reladdr 0xB8 3 2 C CJNE R1,#data8,reladdr 0xB9 3 2 C CJNE R2,#data8,reladdr 0xBA 3 2 C CJNE R3,#data8,reladdr 0xBB 3 2 C CJNE R4,#data8,reladdr 0xBC 3 2 C CJNE R5,#data8,rela
8052 Instruction Set CPL Complement Register Syntax CPL operand Instructions OpCode Bytes Cycles Flags CPL A 0xF4 1 1 None CPL C 0xB3 1 1 C CPL bitAddr 0xB2 2 1 None CPL complements operand, leaving the result in operand. If operand is a single bit, the state of the bit is reversed. If operand is the accumulator, all the bits in the accumulator are reversed. This can be thought of as accumulator logical exclusive OR 255, or as 255-accumulator.
8052 Instruction Set DEC Decrement Register Syntax DEC register Instructions OpCode Bytes Cycles Flags DEC A 0x14 1 1 None DEC direct 0x15 2 1 None DEC @R0 0x16 1 1 None DEC @R1 0x17 1 1 None DEC R0 0x18 1 1 None DEC R1 0x19 1 1 None DEC R2 0x1A 1 1 None DEC R3 0x1B 1 1 None DEC R4 0x1C 1 1 None DEC R5 0x1D 1 1 None DEC R6 0x1E 1 1 None DEC R7 0x1F 1 1 None DEC decrements the value of register by 1.
8052 Instruction Set DJNZ Decrement and Jump if Not Zero Syntax DJNZ register,relAddr Instructions OpCode Bytes Cycles Flags DJNZ direct,relAddr 0xD5 3 2 None DJNZ R0,relAddr 0xD8 2 2 None DJNZ R1,relAddr 0xD9 2 2 None DJNZ R2,relAddr 0xDA 2 2 None DJNZ R3,relAddr 0xDB 2 2 None DJNZ R4,relAddr 0xDC 2 2 None DJNZ R5,relAddr 0xDD 2 2 None DJNZ R6,relAddr 0xDE 2 2 None DJNZ R7,relAddr 0xDF 2 2 None DJNZ decrements the value of register by 1.
8052 Instruction Set INC Increment Reister Syntax INC register Instructions OpCode Bytes Cycles Flags INC A 0x04 1 1 None INC direct 0x05 2 1 None INC @R0 0x06 1 1 None INC @R1 0x07 1 1 None INC R0 0x08 1 1 None INC R1 0x09 1 1 None INC R2 0x0A 1 1 None INC R3 0x0B 1 1 None INC R4 0x0C 1 1 None INC R5 0x0D 1 1 None INC R6 0x0E 1 1 None INC R7 0x0F 1 1 None INC DPTR 0xA3 1 2 None INC increments the value of register by 1.
8052 Instruction Set JB Jump if Bit Set Syntax JB bitAddr,relAddr Instructions OpCode Bytes Cycles Flags 0x20 3 2 None JB bitAddr,relAddr JB branches to the address indicated by relAddr if the bit indicated by bitAddr is set. If the bit is not set, program execution continues with the instruction following the JB instruction.
8052 Instruction Set JMP Jump to Data Pointer + Accumulator Syntax JMP @A+DPTR Instructions JMP @A+DPTR OpCode Bytes Cycles Flags 0x73 1 2 None JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the value of the accumulator.
8052 Instruction Set JNZ Jump if Accumulator Not Zero Syntax JNZ reladdr Instructions OpCode Bytes Cycles Flags JNZ relAddr 0x70 2 2 None JNZ branches to the address indicated by relAddr if the accumulator contains any value except 0. If the value of the accumulator is zero, program execution continues with the instruction following the JNZ instruction.
8052 Instruction Set MOV Move Memory Into/Out of Accumulator Syntax MOV operand1, operand2 Instructions OpCode Bytes Cycles Flags MOV A,#data8 0x74 2 1 None MOV A,@R0 0xE6 1 1 None MOV A,@R1 0xE7 1 1 None MOV @R0,A 0xF6 1 1 None MOV @R1,A 0xF7 1 1 None MOV A,R0 0xE8 1 1 None MOV A,R1 0xE9 1 1 None MOV A,R2 0xEA 1 1 None MOV A,R3 0xEB 1 1 None MOV A,R4 0xEC 1 1 None MOV A,R5 0xED 1 1 None MOV A,R6 0xEE 1 1 None MOV A,R7 0xEF 1 1 None M
8052 Instruction Set MOV Move into/out of Internal RAM Syntax MOV operand1,operand2 Instructions OpCode Bytes Cycles Flags 0x76 2 1 None MOV @R1,#data8 0x77 2 1 None MOV @R0,direct 0xA6 2 2 None MOV @R1,direct 0xA7 2 2 None MOV R0,#data8 0x78 2 1 None MOV R1,#data8 0x79 2 1 None MOV R2,#data8 0x7A 2 1 None MOV R3,#data8 0x7B 2 1 None MOV R4,#data8 0x7C 2 1 None MOV R5,#data8 0x7D 2 1 None MOV R6,#data8 0x7E 2 1 None MOV R7,#data8 0x7F 2 1 No
8052 Instruction Set MOV DPTR Move value into DPTR Syntax MOV DPTR,#data16 Instructions MOV DPTR,#data16 OpCode Bytes Cycles Flags 0x90 3 2 None Sets the value of the data pointer (DPTR) to the value data16. See also: MOVX, MOVC MOVC Move Code Byte to Accumulator Syntax MOVC A,@A+register Instructions OpCode Bytes Cycles Flags MOVC A,@A+DPTR 0x93 1 2 None MOVC A,@A+PC 0x83 1 1 None MOVC moves a byte from code memory into the accumulator.
8052 Instruction Set MUL Multiply Accumulator by B Syntax MUL AB Instructions MUL AB OpCode 0xA4 Bytes 1 Cycles 4 Flags C, OV MUL multiplies the unsigned value in the accumulator by the unsigned value in the B register. The least-significant byte of the result is placed in the accumulator and the most-significant byte is placed in the B register. The carry (C) flag is always cleared. The overflow (OV) flag is set if the result is greater than 255 (if the most-significant byte is not zero).
8052 Instruction Set ORL Bitwise OR Syntax Syntax: ORL operand1,operand2 Instructions ORL direct,A ORL direct,#data8 ORL A,#data8 ORL A,direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 ORL C,bitAddr ORL C,/bitAddr OpCode 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x72 0xA0 Bytes 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 Cycles 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 Flags None None None None None None None None None None None None None None
8052 Instruction Set POP Pop Value from Stack Syntax POP register Instructions OpCode Bytes Cycles Flags 0xD0 2 2 None POP direct POP pops the last value placed on the stack into the direct address specified. In other words, POP will load direct with the value of the internal RAM address pointed to by the current stack pointer. The stack pointer is then decremented by 1. Note: The address of direct must be an internal RAM or SFR address.
8052 Instruction Set RET Return from Subroutine Syntax RET Instructions RET OpCode Bytes Cycles Flags 0x22 1 2 None RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution continues at the address that is calculated by POPping the top-most two bytes off the stack. The most-significant byte is POPped off the stack first, followed by the least-significant byte.
8052 Instruction Set RLC – Rotate Accumulator Left Through Carry Syntax RLC A Instructions OpCode Bytes Cycles Flags 0x33 1 1 C RLC A RLC shifts the bits of the accumulator to the left. The left-most bit (bit 7) of the accumulator is loaded into the carry flag, and the original carry flag is loaded into bit 0 of the accumulator.
8052 Instruction Set SJMP Short Jump Syntax SJMP relAddr Instructions OpCode Bytes Cycles Flags SJMP relAddr 0x80 2 2 None SJMP jumps unconditionally to the address specified relAddr. RelAddr must be within −128 or +127 bytes of the instruction that follows the SJMP instruction.
8052 Instruction Set SWAP Subtract Accumulator Nibbles Syntax SWAP A Instructions SWAP A OpCode Bytes Cycles Flags 0xC4 1 1 None SWAP swaps bits 0−3 of the accumulator with bits 4−7 of the accumulator. This instruction is identical to executing RR A or RL A four times.
8052 Instruction Set XRL Bitwise Exclusive OR Syntax XRL operand1,operand2 Instructions OpCode Bytes Cycles Flags XRL direct,A 0x62 2 1 None XRL direct,#data8 0x63 3 2 None XRL A,#data8 0x64 2 1 None XRL A,direct 0x65 2 1 None XRL A,@R0 0x66 1 1 None XRL A,@R1 0x67 1 1 None XRL A,R0 0x68 1 1 None XRL A,R1 0x69 1 1 None XRL A,R2 0x6A 1 1 None XRL A,R3 0x6B 1 1 None XRL A,R4 0x6C 1 1 None XRL A,R5 0x6D 1 1 None XRL A,R6 0x6E 1 1 None XR
8052 Instruction Set UNDEFINED Undefined Instruction Syntax ??? Instructions ??? OpCode Bytes Cycles Flags 0xA5 1 1 C The undefined instruction is, as the name suggests, not a documented instruction. The 8052 supports 255 instructions and OpCode 0xA5 is the single opcode that is not used by any documented function. It is not recommended that it be executed because it is not documented nor defined.
Appendix F " )# 0 0 ! Appendix F defines the MSC1210 bit-addressable special function registers (SFRs) in alphabetical order. Topic F.1 Page Bit-Addressable SFRs (alphabetical) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Addressable SFRs (alphabetical) F.1 Bit Addressable SFRs (alphabetical) Enable Interrupt Control (EICON) SFR Name: EICON SFR Address: D8H Bit-Addressable: Yes Bit Definitions: Name Bit Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMOD1 — EAI AI WDTI — — — DFH DEH DDH DCH DBH DAH D9H D8H SMOD1—Serial Port 1 Mode. 0 = Normal baud rate for serial port 1, 1 = Serial port 1 baud rate doubled. EAI—Enable Auxiliary Interrupt. 1 = Interrupt enabled.
Bit Addressable SFRs (alphabetical) Extended Interrupt Priority (EIP) SFR Name: EIE SFR Address: F8H Bit-Addressable: Yes Bit Definitions: bit 7 Name Bit Address bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 — — — PWDI PX5 PX4 PX3 PX2 FFH FEH FDH FCH FBH FAH F9H F8H PWDI—Watchdog Interrupt Priority. 1 = Watchdog interrupt high-level priority, 0 = low-level priority. PX5—External 5 Interrupt Priority. 1 = External 5 interrupt high-level priority, 0 = low-level priority.
Bit Addressable SFRs (alphabetical) INTERRUPT PRIORITY (IP) SFR Name: IP SFR Address: B8H Bit−Addressable: Yes Bit−Definitions: bit 7 Name Bit Address bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 — — PT2 PS PT1 PX1 PT0 PX0 BFH BEH BDH BCH BBH BAH B9H B8H PT2—Priority Timer 2 Interupt. 1 = high-priority interrupt, 0 = low-priority interrupt. PS—Priority Serial Interupt. 1 = high-priority interrupt, 0 = low-priority interrupt. PT1—Priority Timer 1 Interupt.
Bit Addressable SFRs (alphabetical) Port 1 (P1) SFR Name: P1 SFR Address: 90H Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 T2EX T2 Bit Address 97H 96H 95H 94H 93H 92H 91H 90H T2EX—Timer 2 Capture/Reload. Optional external capturing or reloading of timer 2. T2—Timer 2 External Input. Optionally used to control timer/counter 2 via external source.
Bit Addressable SFRs (alphabetical) Port 3 (P3) SFR Name: P3 SFR Address: B0H Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name RD WR T1 T0 INT1 INT0 TXD RXD Bit Address B7H B6H B5H B4H B3H B2H B1H B0H RD—Read Strobe. 0 = external memory read strobe. WR—Write Strobe. 0 = external memory write strobe. T1—Timer/Counter 1 External Input. Optionally used to control timer/counter 1 via external source. T0—Timer/Counter 0 External Input.
Bit Addressable SFRs (alphabetical) Program Status Word (PSW) SFR Name: PSW SFR Address: D0H Bit−Addressable: Yes Bit−Definitions: Name Bit Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CY AC F0 RS1 RS0 OV — P D7H D6H D5H D4H D3H D2H D1H D0H CY—Carry Flag. Set or cleared by instructions ADD, ADDC, SUBB, MUL, and DIV. AC—Auxiliary Carry. Set or cleared by instructions ADD, ADDC. F0—Flag 0. General flag available to developer for user-defined purposes.
Bit Addressable SFRs (alphabetical) Serial Control (SCON) SFR Name: SCON SFR Address: 98H Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Address 9FH 9EH 9DH 9CH 9BH 9AH 99H 98H SM0/SM1– Serial Mode. These two bits, taken together, select the serial mode in which the serial port will operate.
Bit Addressable SFRs (alphabetical) Timer Control (TCON) SFR Name: TCON SFR Address: 88H Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Address 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H TF1—Timer 1 Overflow Flag. This bit is set by the MCU when Timer 1 overflows from FFFFH back to 0000H. Cleared by software, or cleared automatically by hardware if a Timer 1 interrupt is triggered. TR1—Timer 1 Run Control.
Bit Addressable SFRs (alphabetical) Timer 2 Control (T2CON) SFR Name: T2CON SFR Address: C8H Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2C Bit Address CFH CEH CDH CCH CBH CAH C9H C8H TF2—Timer 2 Overflow Flag. This bit is set by the MCU when Timer 2 overflows from FFFFH back to 0000H. When enabled, this bit causes a Timer 2 interrupt. Cleared by software.
Appendix G '# 0 ) , 0( ! Appendix G lists an alphabetical cross-reference of the MSC1210 special function registers (SFRs) and their addresses. Topic G.1 Page SFR/Address Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR/Address Cross-Reference G.
SFR/Address Cross-Reference MPAGE Memory Page 92H MSECH Millisecond Counter High FDH MSECL Millisecond Counter Low FCH MSINT Microseconds Interrupt FaH MWS Memory Write Select 8FH OCH ADC Offset Calibration High D3H OCL ADC Offset Calibration Low D1H OCM ADC Offset Calibration Middle D2H ODAC Offset DAC E6H P0 Port 0 80H P0DDRH Port 0 Data Direction High ADH P0DDRL Port 0 Data Direction Low ACH P1 Port 1 90H P1DDRH Port 1 Data Direction High AFH P1DDRL Port 1 Data
SFR/Address Cross-Reference SPIRCON SPI Receive Control 9CH SPISTART SPI Buffer Start Address 9EH SPITCON SPI Transmit Control 9DH SRST System Reset F7H SSCON Summation/Shifter Control E1H SSUMR0 Summation Register 0 E2H SSUMR1 Summation Register 1 E3H SSUMR2 Summation Register 2 E4H SSUMR3 Summation Register 3 E5H T2CON Timer 2 Control C8H TCON Timer Control 88H TH0 Timer 0 High 8CH TH1 Timer 1 High 8DH TH2 Timer 2 High CDH TL0 Timer 0 Low 8AH TL1 Timer 1 Low
