User’s Guide 2005 Mixed Signal Products SLAU056E
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Related Documentation From Texas Instruments Preface Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family.
Glossary Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www.ti.
Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 (w) No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0.
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Contents Contents 1 Introduction 1.1 Architecture 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Flash/ROM . . . . . . . . . . . . . . . . . . . .
Contents 3.4 3.3.5 Indirect Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Indirect Autoincrement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.7 Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.
Contents 7 Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Operand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 11 Basic Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Basic Timer1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Basic Timer1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Basic Timer1 Counter One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 15 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 19 LCD_A Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1 LCD_A Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 LCD_A Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.2.1 LCD Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 22 SD16_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1 SD16_A Introduction 22-2 22.2 SD16_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.1 ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.2 Analog Input Range and PGA . . . . .
Chapter 1 Introduction This chapter describes the architecture of the MSP430. Topic Page 1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x4xx family include: - Ultralow-power architecture extends battery life J 0.1-µA RAM retention J 0.
Embedded Emulation Figure 1−1. MSP430 Architecture ACLK Clock System SMCLK Flash/ ROM RAM Peripheral Peripheral Peripheral RISC CPU 16-Bit JTAG/Debug MCLK MAB 16-Bit MDB 16-Bit Bus Conv. MDB 8-Bit JTAG ACLK SMCLK Watchdog Peripheral Peripheral Peripheral Peripheral 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources.
Address Space 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is 64 KB with future expansion planned. Figure 1−2.
Address Space 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules should be accessed with byte instructions.
Chapter 2 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, and operating modes. Topic Page 2.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.
System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated. Figure 2−1.
System Reset and Initialization 2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the VCC terminal. The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed. The operating levels are shown in Figure 2−2. The POR signal becomes active when VCC crosses the VCC(start) level.
System Reset and Initialization 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST/NMI pin is configured in the reset mode. - I/O pins are switched to input mode as described in the Digital I/O chapter. - Other peripheral modules and registers are initialized as described in their respective chapters in this manual. - Status register (SR) is reset. - The watchdog timer powers up active in watchdog mode.
System Reset and Initialization 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously. There are three types of interrupts: - System reset - (Non)-maskable NMI - Maskable Figure 2−3.
System Reset and Initialization 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset. Program execution begins at the address stored in the (non)-maskable interrupt vector, 0FFFCh.
System Reset and Initialization Figure 2−4. Block Diagram of (Non)-Maskable Interrupt Sources ACCV S ACCVIFG FCTL1.1 ACCVIE IE1.5 Clear Flash Module PUC RST/NMI POR PUC KEYV VCC PUC System Reset Generator POR S NMIIFG NMIRS IFG1.4 WDTTMSEL WDTNMIES WDTNMI Clear WDTQn EQU PUC POR PUC NMIIE S IE1.4 WDTIFG IRQ Clear IFG1.0 Clear PUC WDT Counter OSCFault POR S OFIFG IFG1.1 IRQA OFIE WDTTMSEL WDTIE IE1.1 Clear IE1.
System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator. The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault. A PUC signal can trigger an oscillator fault, because the PUC switches the LFXT1 to LF mode, therefore switching off the HF mode.
System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2−5. Figure 2−5.
System Reset and Initialization Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual. 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-maskable interrupts to be requested.
System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−7. 1) The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine.
System Reset and Initialization 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in Table 2−1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine. See the device-specific data sheet for the complete interrupt vector list. Table 2−1.
Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−9. The operating modes take into account three different needs: - Ultralow-power - Speed and data throughput - Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2−8. ICC/ µA @ 1 MHz Figure 2−8.
Operating Modes Figure 2−9.
Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: - Enter interrupt service routine: J The PC and SR are stored on the stack J The CPUOFF, SCG1, and OSCOFF bits are automatically reset - Options for returning from the interrupt service routine: J The original SR is popped from the stack, restoring the previous operating mode.
Principles for Low-Power Applications 2.4 Principles for Low-Power Applications Often, the most important factor for reducing power consumption is using the MSP430’s clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 µA typical with both a real-time clock function and all interrupts active. A 32-kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO (normally off) which has a 6-µs wake-up. - Use interrupts to wake the processor and control program flow.
Chapter 3 This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic Page 3.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 Instruction Set . . . . . . . . . . .
CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: - RISC architecture with 27 instructions and 7 addressing modes. - Orthogonal architecture with every instruction usable with every addressing mode.
CPU Introduction Figure 3−1.
CPU Registers 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses.
CPU Registers 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 3−3 shows the SP. The SP is initialized into RAM by the user, and is aligned to even addresses. Figure 3−4 shows stack usage. Figure 3−3.
CPU Registers 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 3−6 shows the SR bits. Figure 3−6. Status Register Bits 9 15 Reserved 8 V 7 SCG1 0 OSC CPU SCG0 GIE OFF OFF N Z C Table 3−1 describes the status register bits. Table 3−1.
CPU Registers 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3−2. Table 3−2.
CPU Registers 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions as shown in Figure 3−7. Figure 3−7.
Addressing Modes 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3−3 describe the contents of the As (source) and Ad (destination) mode bits. Table 3−3.
Addressing Modes 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Assembler Code MOV Content of ROM R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected.
Addressing Modes 3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Assembler Code MOV Content of ROM 2(R5),6(R6) MOV X(R5),Y(R6) X=2 Y=6 Length: Two or three words Operation: Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected.
Addressing Modes 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(PC),Y(PC) X = EDE − PC Y = TONI − PC Length: Two or three words Operation: Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses.
Addressing Modes 3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Assembler Code MOV &EDE,&TONI Content of ROM MOV X(0),Y(0) X = EDE Y = TONI Length: Two or three words Operation: Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses.
Addressing Modes 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Assembler Code MOV @R10,0(R11) MOV @R10,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Comment: Valid only for source operand. The substitute for destination operand is 0(Rd). Example: MOV.
Addressing Modes 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Assembler Code MOV Content of ROM @R10+,0(R11) MOV @R10+,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11).
Addressing Modes 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10.Immediate Mode Description Assembler Code MOV Content of ROM #45h,TONI MOV @PC+,X(PC) 45 X = TONI − PC Length: Two or three words It is one word less if a constant of CG1 or CG2 can be used. Operation: Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI.
Instruction Set 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction. There is no code or performance penalty for using emulated instruction.
Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format 15 14 13 12 11 10 9 8 S-Reg Op-code 7 6 Ad B/W 5 4 3 2 As 1 0 D-Reg Table 3−11 lists and describes the double operand instructions. Table 3−11. Double Operand Instructions Mnemonic S-Reg, D-Reg Operation Status Bits V N Z C MOV(.B) src,dst src → dst − − − − ADD(.
Instruction Set 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format 15 14 13 12 11 10 9 8 7 Op-code 6 5 B/W 4 3 Ad 2 1 0 D/S-Reg Table 3−12 lists and describes the single operand instructions. Table 3−12.Single Operand Instructions S-Reg, D-Reg Operation RRC(.B) dst C → MSB →.......LSB → C * * * * RRA(.B) dst MSB → MSB →....LSB → C 0 * * * PUSH(.
Instruction Set 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format 15 14 13 Op-code 12 11 10 9 8 7 C 6 5 4 3 2 1 0 10-Bit PC Offset Table 3−13 lists and describes the jump instructions. Table 3−13.
Instruction Set ADC[.W] ADC.B Add carry to destination Add carry to destination Syntax ADC ADC.B Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
Instruction Set ADD[.W] ADD.B Add source to destination Add source to destination Syntax ADD ADD.B Operation src + dst −> dst Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R5 is increased by 10. The jump to TONI is performed on a carry. ADD.
Instruction Set ADDC[.W] ADDC.B Add source and carry to destination Add source and carry to destination Syntax ADDC ADDC.B Operation src + dst + C −> dst Description The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Instruction Set AND[.W] AND.B Source AND destination Source AND destination Syntax AND AND.B Operation src .AND. dst −> dst Description The source operand and the destination operand are logically ANDed. The result is placed into the destination. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The bits set in R5 are used as a mask (#0AA55h) for the word addressed by TOM. If the result is zero, a branch is taken to label TONI.
Instruction Set BIC[.W] BIC.B Clear bits in destination Clear bits in destination Syntax BIC BIC.B Operation .NOT.src .AND. dst −> dst Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The six MSBs of the RAM word LEO are cleared. BIC Example src,dst src,dst or BIC.
Instruction Set BIS[.W] BIS.B Set bits in destination Set bits in destination Syntax BIS BIS.B Operation src .OR. dst −> dst Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The six LSBs of the RAM word TOM are set. BIS Example or BIS.
Instruction Set BIT[.W] BIT.B Test bits in destination Test bits in destination Syntax BIT Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example If bit 9 of R8 is set, a branch is taken to label TOM.
Instruction Set * BR, BRANCH Branch to .......... destination Syntax BR Operation dst −> PC Emulation MOV Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status Bits Status bits are not affected. Example Examples for all addressing modes are given. 3-28 dst dst,PC BR #EXEC ;Branch to label EXEC or direct branch (e.g.
Instruction Set CALL Subroutine Syntax CALL dst Operation dst SP − 2 PC tmp −> tmp −> SP −> @SP −> PC dst is evaluated and stored PC updated to TOS dst saved to PC Description A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status Bits Status bits are not affected.
Instruction Set * CLR[.W] * CLR.B Clear destination Clear destination Syntax CLR CLR.B Operation 0 −> dst Emulation MOV MOV.B Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. CLR Example #0,dst #0,dst TONI ; 0 −> TONI R5 RAM byte TONI is cleared. CLR.B 3-30 or CLR.W dst Register R5 is cleared.
Instruction Set * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation BIC Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12.
Instruction Set * CLRN Clear negative bit Syntax CLRN Operation 0→N or (.NOT.src .AND. dst −> dst) Emulation BIC Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The Negative bit in the status register is cleared.
Instruction Set * CLRZ Clear zero bit Syntax CLRZ Operation 0→Z or (.NOT.src .AND. dst −> dst) Emulation BIC Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The zero bit in the status register is cleared.
Instruction Set CMP[.W] CMP.B Compare source and destination Compare source and destination Syntax CMP CMP.B Operation dst + .NOT.src + 1 or (dst − src) Description The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Instruction Set * DADC[.W] * DADC.B Add carry decimally to destination Add carry decimally to destination Syntax DADC DADC.B Operation dst + C −> dst (decimally) Emulation DADD DADD.B Description The carry bit (C) is added decimally to the destination.
Instruction Set DADD[.W] DADD.B Source and carry added decimally to destination Source and carry added decimally to destination Syntax DADD DADD.B Operation src + dst + C −> dst (decimally) Description The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C) are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost.
Instruction Set * DEC[.W] * DEC.B Decrement destination Decrement destination Syntax DEC DEC.B Operation dst − 1 −> dst Emulation Emulation SUB SUB.B Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 1 dst dst or DEC.
Instruction Set * DECD[.W] * DECD.B Double-decrement destination Double-decrement destination Syntax DECD DECD.B Operation dst − 2 −> dst Emulation Emulation SUB SUB.B Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R10 is decremented by 2. dst dst or DECD.
Instruction Set * DINT Disable (general) interrupts Syntax DINT Operation 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst −> dst) Emulation BIC Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is reset. OSCOFF and CPUOFF are not affected.
Instruction Set * EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation BIS Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is set. OSCOFF and CPUOFF are not affected. Example The general interrupt enable (GIE) bit in the status register is set.
Instruction Set * INC[.W] * INC.B Increment destination Increment destination Syntax INC INC.B Operation dst + 1 −> dst Emulation ADD Description The destination operand is incremented by one. The original contents are lost.
Instruction Set * INCD[.W] * INCD.B Double-increment destination Double-increment destination Syntax INCD INCD.B Operation dst + 2 −> dst Emulation Emulation ADD ADD.B Example The destination operand is incremented by two. The original contents are lost.
Instruction Set * INV[.W] * INV.B Invert destination Invert destination Syntax INV INV.B Operation .NOT.dst −> dst Emulation Emulation XOR XOR.B Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT.
Instruction Set JC JHS Jump if carry set Jump if higher or same Syntax JC JHS Operation If C = 1: PC + 2 × offset −> PC If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed. JC (jump if carry/higher or same) is used for the comparison of unsigned numbers (0 to 65536).
Instruction Set JEQ, JZ Jump if equal, jump if zero Syntax JEQ Operation If Z = 1: PC + 2 × offset −> PC If Z = 0: execute following instruction Description The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status Bits Status bits are not affected. Example Jump to address TONI if R7 contains zero.
Instruction Set JGE Jump if greater or equal Syntax JGE Operation If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed.
Instruction Set JL Jump if less Syntax JL Operation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed. label This allows comparison of signed integers.
Instruction Set JMP Jump unconditionally Syntax JMP Operation PC + 2 × offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces the BRANCH instruction in the range of −511 to +512 words relative to the current program counter.
Instruction Set JN Jump if negative Syntax JN Operation if N = 1: PC + 2 × offset −> PC if N = 0: execute following instruction Description The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status Bits Status bits are not affected. Example The result of a computation in R5 is to be subtracted from COUNT.
Instruction Set JNC JLO Jump if carry not set Jump if lower Syntax JNC JLO Operation if C = 0: PC + 2 × offset −> PC if C = 1: execute following instruction Description The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed. JNC (jump if no carry/lower) is used for the comparison of unsigned numbers (0 to 65536).
Instruction Set JNE JNZ Jump if not equal Jump if not zero Syntax JNE JNZ Operation If Z = 0: PC + 2 × offset −> PC If Z = 1: execute following instruction Description The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status Bits Status bits are not affected. Example Jump to address TONI if R7 and R8 have different contents.
Instruction Set MOV[.W] MOV.B Move source to destination Move source to destination Syntax MOV MOV.B Operation src −> dst Description The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The contents of table EDE (word data) are copied to table TOM. The length of the tables must be 020h locations.
Instruction Set * NOP No operation Syntax NOP Operation None Emulation MOV Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected.
Instruction Set * POP[.W] * POP.B Pop word from stack to destination Pop byte from stack to destination Syntax POP POP.B Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation Emulation MOV MOV.B Description The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status Bits Status bits are not affected. Example The contents of R7 and the status register are restored from the stack.
Instruction Set PUSH[.W] PUSH.B Push word onto stack Push byte onto stack Syntax PUSH PUSH.B Operation SP − 2 → SP src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The contents of the status register and R8 are saved on the stack. PUSH PUSH Example src src or SR R8 PUSH.
Instruction Set * RET Return from subroutine Syntax RET Operation @SP→ PC SP + 2 → SP Emulation MOV Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status Bits Status bits are not affected.
Instruction Set RETI Return from interrupt Syntax RETI Operation TOS SP + 2 TOS SP + 2 Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. → SR → SP → PC → SP The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow.
Instruction Set * RLA[.W] * RLA.B Rotate left arithmetically Rotate left arithmetically Syntax RLA RLA.B Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 Emulation ADD ADD.B Description The destination operand is shifted left one position as shown in Figure 3−14. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. dst dst or RLA.
Instruction Set * RLC[.W] * RLC.B Rotate left through carry Rotate left through carry Syntax RLC RLC.B Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C Emulation ADDC Description The destination operand is shifted left one position as shown in Figure 3−15. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). dst dst or RLC.W dst dst,dst Figure 3−15.
Instruction Set RRA[.W] RRA.B Rotate right arithmetically Rotate right arithmetically Syntax RRA RRA.B Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, Description The destination operand is shifted right one position as shown in Figure 3−16. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB. dst dst or RRA.W dst LSB −> C Figure 3−16.
Instruction Set RRC[.W] RRC.B Rotate right through carry Rotate right through carry Syntax RRC RRC Operation C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). dst dst or RRC.W dst Figure 3−17.
Instruction Set * SBC[.W] * SBC.B Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination Syntax SBC SBC.B Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC SUBC.B Description The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost.
Instruction Set * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation BIS Description The carry bit (C) is set. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Instruction Set * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation BIS Description The negative bit (N) is set. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Instruction Set * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation BIS Description The zero bit (Z) is set. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Instruction Set SUB[.W] SUB.B Subtract source from destination Subtract source from destination Syntax SUB SUB.B Operation dst + .NOT.src + 1 −> dst or [(dst − src −> dst)] Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost.
Instruction Set SUBC[.W]SBB[.W] SUBC.B,SBB.B Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination Syntax SUBC SBB SUBC.B Operation dst + .NOT.src + C −> dst or (dst − src − 1 + C −> dst) Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost.
Instruction Set SWPB Swap bytes Syntax SWPB Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. dst Figure 3−18. Destination Operand Byte Swap 15 8 7 Example MOV SWPB Example ; 0100000010111111 −> R7 ; 1011111101000000 in R7 The value in R5 is multiplied by 256. The result is stored in R5,R4.
Instruction Set SXT Extend Sign Syntax SXT Operation Bit 7 −> Bit 8 ......... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. dst Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if result is not zero, reset otherwise (.NOT. Zero) Reset Figure 3−19.
Instruction Set * TST[.W] * TST.B Test destination Test destination Syntax TST TST.B Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP CMP.B Description The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS.
Instruction Set XOR[.W] XOR.B Exclusive OR of source with destination Exclusive OR of source with destination Syntax XOR XOR.B Operation src .XOR. dst −> dst Description The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. Status Bits N: Z: C: V: Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The bits set in R6 toggle the bits in the RAM word TONI. XOR.
Instruction Set 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles Table 3−14 lists the CPU cycles for interrupt overhead and reset. Table 3−14.Interrupt and Reset Cycles No.
Instruction Set Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3−16.Format I Instruction Cycles and Lengths No.
Instruction Set 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in Table 3−17. Figure 3−20. Core Instruction Map 000 0xxx 4xxx 8xxx Cxxx 1xxx 14xx 18xx 1Cxx 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx 3-74 040 080 0C0 RRC RRC.B SWPB 100 RRA 140 180 RRA.B SXT 1C0 200 240 280 PUSH PUSH.B CALL JNE/JNZ JEQ/JZ JNC JC JN JGE JL JMP MOV, MOV.B ADD, ADD.
Instruction Set Table 3−17.MSP430 Instruction Set Mnemonic V N Z ADC(.B)† dst Description Add C to destination dst + C → dst * * * C * ADD(.B) src,dst Add source to destination src + dst → dst * * * * ADDC(.B) src,dst Add source and C to destination src + dst + C → dst * * * * AND(.B) src,dst AND source and destination src .and. dst → dst 0 * * * BIC(.B) src,dst Clear bits in destination .not.src .and. dst → dst − − − − BIS(.
Chapter 4 The FLL+ clock module provides the clocks for MSP430x4xx devices. This chapter discusses the FLL+ clock module. The FLL+ clock module is implemented in all MSP430x4xx devices. Topic Page 4.1 FLL+ Clock Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 FLL+ Clock Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 FLL+ Clock Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 FLL+ Clock Module Introduction The frequency-locked loop (FLL+) clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware. The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch crystal frequency.
Figure 4−1.
Figure 4−2.
FLL+ Clock Module Operation 4.2 FLL+ Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK and SMCLK will stabilize to 1.048576 MHz. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable components of the FLL+ clock module. See Chapter System Resets, Interrupts and Operating Modes.
FLL+ Clock Module Operation 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connects to XIN and XOUT without any external components. The LFXT1 oscillator supports high-speed crystals or resonators when in HF mode (XTS_FLL = 1). The high-speed crystal or resonator connects to XIN and XOUT. LFXT1 may be used with an external clock signal on the XIN pin when XTS_FLL = 1.
FLL+ Clock Module Operation 4.2.4 Digitally-Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N, the lowest 7 bits of the SCFQCTL register. The DCOPLUS bit sets the fDCOCLK frequency to fDCO or fDCO/D. The FLLDx bits configure the divider, D, to 1, 2, 4 or 8. By default, DCOPLUS = 0 and D = 2 providing a clock frequency of fDCO/2 on fDCOCLK.
FLL+ Clock Module Operation 4.2.6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy, reducing electromagnetic interference (EMI). The modulator mixes the two adjacent frequencies across 32 DCOCLK clock cycles. The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate. The modulator settings and DCO control are automatically controlled by the FLL hardware.
FLL Operation from Low-Power Modes- 4.2.7 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCG0 = 1. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized. The DCO modulator is disabled when SCFQ_M = 1. When the DCO modulator is disabled, the DCOCLK is adjusted to the nearest of the available DCO taps. 4.2.
Buffered Clock Output 4.2.10 FLL+ Fail-Safe Operation The FLL+ module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 4−4.
FLL+ Clock Module Registers 4.3 FLL+ Clock Module Registers The FLL+ registers are listed in Table 4−2. Table 4−2.
FLL+ Clock Module Registers SCFQCTL, System Clock Control Register 7 6 5 4 3 SCFQ_M 2 1 0 rw−1 rw−1 rw−1 N rw−0 rw−0 rw−0 rw−1 rw−1 SCFQ_M Bit 7 Modulation. This enables or disables modulation 0 Modulation enabled 1 Modulation disabled N Bits 6-0 Multiplier. These bits set the multiplier value for the DCO. N must be > 0 or unpredictable operation will result.
FLL+ Clock Module Registers SCFI1, System Clock Frequency Integrator Register 1 7 6 5 4 3 2 DCOx rw−0 rw−0 rw−0 1 0 MODx (MSBs) rw−0 rw−0 rw−0 rw−0 rw−0 DCOx Bits 7-3 These bits select the DCO tap and are modified automatically by the FLL+. MODx Bit 2 Most significant modulator bits. Bit 2 is the modulator MSB. These bits affect the modulator pattern. All MODx bits are modified automatically by the FLL+.
FLL+ Clock Module Registers FLL_CTL0, FLL+ Control Register 0 7 6 DCOPLUS XTS_FLL rw−0 rw−0 5 4 XCAPxPF rw−0 3 2 1 0 XT2OF† XT1OF LFOF DCOF r0 r0 r−(1) r−1 rw−0 † Not present in MSP430x41x, MSP430x42x devices DCOPLUS Bit 7 DCO output pre-divider. This bit selects if the DCO output is pre-divided before sourcing MCLK or SMCLK.
FLL+ Clock Module Registers FLL_CTL1, FLL+ Control Register 1 7 6 5 Unused SMCLK OFF† XT2OFF† r0 r0 rw−(1) 4 3 SELMx† rw−(0) 2 1 SELS† rw−(0) rw−(0) 0 FLL_DIVx rw−(0) rw−(0) † Not present in MSP430x41x, MSP430x42x devices. Unused Bit 7 SMCLKOFF Bit 6 SMCLK off. This bit turns off SMCLK. Not present in MSP430x41x, MSPx42x devices. 0 SMCLK is on 1 SMCLK is off XT2OFF Bit 5 XT2 off. This bit turns off the XT2 oscillator. Not present in MSP430x41x, MSPx42x devices.
FLL+ Clock Module Registers IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE rw−0 OFIE Bits 7-2 These bits may be used by other modules. See device-specific datasheet. Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Chapter 5 This chapter describes the operation of the MSP430 flash memory controller. Topic Page 5.1 Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Flash Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3 Flash Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 Flash Memory Registers . . . . . . . . . . . . . . . . . . . .
Flash Memory Introduction 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three registers, a timing generator, and a voltage generator to supply program and erase voltages.
Flash Memory Segmentation 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections. Code or data can be located in either section.
Flash Memory Operation 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU can program its own flash memory.
Flash Memory Operation 5.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 5−1. Table 5−1.
Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes. After the erase cycle completes, the CPU resumes code execution with the instruction following the dummy write.
Flash Memory Operation Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again. If a flash access occurs while BUSY=1, it is an access violation, ACCVIFG will be set, and the erase results will be unpredictable. The flow to initiate an erase from flash from RAM is shown in Figure 5−6. Figure 5−6.
Flash Memory Operation 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 5−1. Interrupts are automatically disabled during a flash write and re-enabled after the write. Any interrupt that occurred during the write will have its associated flag set, and will generate an interrupt request when re-enabled. Table 5−2.
Flash Memory Operation In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 32 of the 35 fFTG cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates. The cumulative programming time, tCPT, must not be exceeded for any block.
Flash Memory Operation Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9. Figure 5−9. Initiating a Byte/Word Write from RAM Disable watchdog yes BUSY = 1 Setup flash controller and set WRT=1 Write byte or word yes BUSY = 1 Set WRT=0, LOCK = 1 re-enable watchdog ; Byte/word write from RAM. 514 kHz < SMCLK < 952 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0.
Flash Memory Operation Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time tCPT must not be exceeded for any block during a block write. A block write cannot be initiated from within flash memory. The block write must be initiated from RAM only.
Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example. Figure 5−11.
Flash Memory Operation ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. ; 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #32,R5 ; Use as write counter MOV #0F000h,R6 ; Write pointer MOV L1 BIT JNZ MOV MOV MOV L2 MOV L3 BIT JZ INCD DEC JNZ MOV L4 BIT JNZ MOV ...
Flash Memory Operation 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable. Also if a write to flash is attempted with WRT=0, the ACCVIFG interrupt flag is set, and the flash memory is unaffected.
Flash Memory Operation 5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The result of the intended operation is unpredictable. 5.3.
Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals (5 signals on 20- and 28-pin devices), ground and optionally VCC and RST/NMI. The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible. Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash-Based MSP430 Using the JTAG Interface at www.
Flash Memory Registers 5.4 Flash Memory Registers The flash memory registers are listed in Table 5−4. Table 5−4.
Flash Memory Registers FCTL1, Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 6 5 4 3 2 1 0 BLKWRT WRT Reserved Reserved Reserved MERAS ERASE Reserved rw−0 rw−0 r0 r0 r0 rw−0 rw−0 r0 FRKEY/ FWKEY Bits 15-8 FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. BLKWRT Bit 7 Block write mode. WRT must also be set for block write mode. BLKWRT is automatically reset when EMEX is set.
Flash Memory Registers FCTL2, Flash Memory Control Register 15 14 13 12 11 10 9 8 2 1 0 rw−0 rw-1 rw−0 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 FSSELx rw−0 FNx rw−1 rw-0 rw-0 rw-0 FWKEYx Bits 15-8 FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. FSSELx Bits 7−6 Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK FNx Bits 5-0 Flash controller clock divider.
Flash Memory Registers FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 Reserved Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY r0 r0 rw-0 rw-1 r-1 rw−0 rw-(0) r(w)−0 FWKEYx Bits 15-8 FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. Reserved Bits 7-6 Reserved. Always read as 0.
Flash Memory Registers IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE rw−0 ACCVIE Bits 7-6, 4-0 These bits may be used by other modules. See device-specific datasheet. Bit 5 Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Chapter 6 This chapter describes the operation of the SVS. The SVS is implemented in all MSP430x4x devices. Topic Page 6.1 SVS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2 6.2 SVS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4 6.3 SVS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVS Introduction 6.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
SVS Introduction Figure 6−1. SVS Block Diagram VCC AVCC Brownout Reset D AVCC G S SVSIN ~ 50us 1111 1101 − SVS_POR + 1100 tReset ~ 50us 0011 0010 SVSOUT 1.
SVS Operation 6.2 SVS Operation The SVS detects if the AVCC voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 6.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V(SVS_IT−)) for comparison with AVCC. The SVS is off when VLDx = 0 and on when VLDx > 0. The SVSON bit does not turn on the SVS.
SVS Operation 6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented to allows the SVS circuitry to settle. During each delay, the SVS will not set SVSFG. The delays, td(SVSon) and tsettle, are shown in Figure 6−2. The td(SVSon) delay takes affect when VLDx is changed from zero to any non-zero value and is a approximately 50 µs. The tsettle delay takes affect when the VLDx bits change from any non-zero value to any other non-zero value and is a maximum of ~12 µs.
SVS Operation 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVCC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 6−3. Figure 6−3.
SVS Registers 6.3 SVS Registers The SVS registers are listed in Table 6−1. Table 6−1. SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read/write Reset with BOR 056h SVSCTL, SVS Control Register 7 6 5 4 VLDx rw−0† † rw−0† rw−0† rw−0† 3 2 1 0 PORON SVSON SVSOP SVSFG rw−0† r† r† rw−0† Reset by a brownout reset only, not by a POR or PUC. VLDx Bits 7-4 Voltage level detect.
Chapter 7 Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier is implemented in MSP430x44x devices. Topic Page 7.1 Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Multiplier Introduction 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Hardware Multiplier Operation 7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT.
Hardware Multiplier Operation 7.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 7−2. Table 7−2. RESHI Contents Mode RESHI Contents MPY Upper 16-bits of the result MPYS The MSB is the sign of the result. The remaining bits are the upper 15-bits of the result. Two’s complement notation is used for the result.
Hardware Multiplier Operation 7.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. ; 16x16 Unsigned Multiply MOV #01234h,&MPY ; Load first operand MOV #05678h,&OP2 ; Load second operand ; ... ; Process results ; 8x8 Unsigned Multiply. Absolute addressing. MOV.B #012h,&0130h ; Load first operand MOV.
Hardware Multiplier Operation 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers: ; Access MOV MOV MOV NOP MOV MOV 7.2.
Hardware Multiplier Registers 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7−4. Table 7−4.
Chapter 8 The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. The DMA controller is implemented in MSP430FG43x and implements only one DMA channel. Topic Page 8.1 DMA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. MSP430FG43x devices implement only one DMA channel. Therefore some features described in this chapter are not applicable to MSP430FG43x devices. Using the DMA controller can increase the throughput of peripheral modules.
Figure 8−1.
8.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 8−2.
8.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 8−1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer mode is configured independently from the addressing mode. Any addressing mode can be used with any transfer mode. Table 8−1.
Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 8−3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers.
Figure 8−3.
Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring during the block transfer are ignored. The block transfer state diagram is shown in Figure 8−4.
Figure 8−4.
Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared. DMAEN must be set again before another burst-block transfer can be triggered.
Figure 8−5.
8.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place.
Table 8−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2 CCIFG flag will not trigger a transfer. 0010 A transfer is triggered when the TBCCR2 CCIFG flag is set.
8.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit. 8.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0−DMA1−DMA2.
8.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
8.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine. 8.2.
8.2.9 Using the I2C Module with the DMA Controller The I2C module provides two trigger sources for the DMA controller. The I2C module can trigger a transfer when new I2C data is received and the when the transmit data is needed. The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the I2C module. When RXDMAEN = 1, the DMA controller can be used to transfer data from the I2C module after the I2C modules receives data.
8.3 DMA Registers The DMA registers are listed in Table 8−4. Table 8−4.
DMACTL0, DMA Control Register 0 15 14 13 12 11 10 9 8 DMA2TSELx Reserved rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 rw−(0) rw−(0) DMA1TSELx rw−(0) rw−(0) rw−(0) DMA0TSELx rw−(0) rw−(0) rw−(0) Reserved Bits 15−12 Reserved DMA2 TSELx Bits 11−8 DMA trigger select. These bits select the DMA transfer trigger.
DMACTL1, DMA Control Register 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 0 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) Reserved Bits 15−3 Reserved. Read only. Always read as 0. DMA ONFETCH Bit 2 DMA on fetch 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger ROUND ROBIN Bit 1 Round robin.
DMAxCTL, DMA Channel x Control Register 15 14 13 12 DMADTx Reserved 11 10 DMADSTINCRx 9 8 DMASRCINCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DMA DSTBYTE DMA SRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMA ABORT DMAREQ rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bit 15 Reserved DMADTx Bits 14−12 DMA Transfer mode.
DMA SRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte DMA LEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0 Edge sensitive (rising edge) 1 Level sensitive (high level) DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA ABORT Bit 1 DMA Abort.
DMAxDA, DMA Destination Address Register 15 14 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw DMAxDAx rw DMAxDAx rw Bits 15−0 rw rw DMA destination address. The destination address register points to the destination address for single transfers or the first address for block transfers. The DMAxDA register remains unchanged during block and burst-block transfers.
Chapter 9 Digital I/O This chapter describes the operation of the digital I/O ports. Ports P1-P6 are implemented in all MSP430x4xx devices. Topic Page 9.1 Digital I/O Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 Digital I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 Digital I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital I/O Introduction 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal.
Digital I/O Operation 9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. 9.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function.
Digital I/O Operation 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function − I/O port or peripheral module function. Bit = 0: I/O Function is selected for the pin Bit = 1: Peripheral module function is selected for the pin Setting PxSELx = 1 does not automatically set the pin direction.
Digital I/O Operation 9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.
Digital I/O Operation Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags.
Digital I/O Registers 9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6. The digital I/O registers are listed in Table 9−1. Table 9−1.
Chapter 10 The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the watchdog timer. The watchdog timer is implemented in all MSP430x4xx devices, except those with the enhanced watchdog timer, WDT+. The WDT+ is implemented in the MSP430x42x, MSP430FE42x, and MSP430F42x0 devices. Topic Page 10.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.
Watchdog Timer Introduction 10.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
Watchdog Timer Introduction Figure 10−1. Watchdog Timer Block Diagram WDTCTL 4 Int.
Watchdog Timer Operation 10.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register. Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte.
Watchdog Timer Operation 10.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sources a reset vector interrupt. The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset.
Watchdog Timer Operation 10.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured. For example, the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low-power mode 3 because SMCLK is not active in LPM3 and the WDT would not function.
Watchdog Timer Registers 10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10−1. Table 10−1.
Watchdog Timer Registers WDTCTL, Watchdog Timer Register 15 14 13 12 11 10 9 8 1 0 Read as 069h WDTPW, must be written as 05Ah 7 6 5 4 3 2 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 WDTISx rw−0 rw−0 WDTPW Bits 15-8 Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC will be generated. WDTHOLD Bit 7 Watchdog timer hold. This bit stops the watchdog timer.
Watchdog Timer Registers IE1, Interrupt Enable Register 1 7 NMIIE WDTIE 6 5 4 3 2 1 0 NMIIE WDTIE rw−0 rw−0 Bits 7-5 These bits may be used by other modules. See device-specific datasheet. Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Watchdog Timer Registers IFG1, Interrupt Flag Register 1 7 NMIIFG WDTIFG 10-10 6 5 4 3 2 1 0 NMIIFG WDTIFG rw−(0) rw−(0) Bits 7-5 These bits may be used by other modules. See device-specific datasheet. Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Chapter 11 The Basic Timer1 module is two independent, cascadable 8-bit timers. This chapter describes the Basic Timer1. Basic Timer1 is implemented in all MSP430x4xx devices. Topic Page 11.1 Basic Timer1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−2 11.2 Basic Timer1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.3 Basic Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Timer1 Introduction 11.1 Basic Timer1 Introduction The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function.
Basic Timer1 Introduction Figure 11−1.
Basic Timer1 Introduction 11.2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8-bit timers or one 16-bit timer with the BTCTL register. The BTCTL register is an 8-bit, read/write register. Any read or write access must use byte instructions. The Basic Timer1 controls the LCD frame frequency with BTCNT1. 11.2.1 Basic Timer1 Counter One The Basic Timer1 counter one, BTCNT1, is an 8-bit timer/counter directly accessible by software.
Basic Timer1 Introduction 11.2.4 Basic Timer1 Operation: Signal fLCD The LCD controller (but not the LCDA controller) uses the fLCD signal from the BTCNT1 to generate the timing for common and segment lines. ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating fLCD. The fLCD frequency is selected with the BTFRFQx bits and can by ACLK/256, ACLK/128, ACLK/64, or ACLK/32.
Basic Timer1 Introduction 11.3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 11−1. Table 11−1.
Basic Timer1 Introduction BTCTL, Basic Timer1 Control Register 7 6 5 BTSSEL BTHOLD BTDIV rw rw rw 4 3 2 1 BTFRFQx rw 0 BTIPx rw rw rw rw BTSSEL Bit 7 BTCNT2 clock select. This bit, together with the BTDIV bit, selects the clock source for BTCNT2. See the description for BTDIV. BTHOLD Bit 6 Basic Timer1 Hold. 0 BTCNT1 and BTCNT2 are operational 1 BTCNT1 is held if BTDIV=1 BTCNT2 is held BTDIV Bit 5 Basic Timer1 clock divide.
Basic Timer1 Introduction BTCNT1, Basic Timer1 Counter 1 7 6 5 4 3 2 1 0 rw rw rw rw BTCNT1x rw BTCNT1x rw Bits 7−0 rw rw BTCNT1 register. The BTCNT1 register is the count of BTCNT1. BTCNT2, Basic Timer1 Counter 2 7 6 5 4 3 2 1 0 rw rw rw rw BTCNT2x rw BTCNT2x 11-8 rw Bits 7−0 Basic Timer1 rw rw BTCNT2 register. The BTCNT2 register is the count of BTCNT2.
Basic Timer1 Introduction IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 BTIE rw−0 BTIE Bit 7 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled Bits 6-1 These bits may be used by other modules. See device-specific datasheet.
Chapter 12 Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_A. Timer_A3 (three capture/compare registers) is implemented in all MSP430x4xx devices. Timer1_A5 (five capture/compare registers) is also implemented on MSP430x415, MSP430x417, and MSP430xW42x devices. Topic Page 12.1 Timer_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 Timer_A Operation . . . . . . . . . . . . . . . . . .
Timer_A Introduction 12.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three or five capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_A Introduction Figure 12−1.
Timer_A Operation 12.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TAR may be cleared by setting the TACLR bit.
Timer_A Operation 12.2.2 Starting the Timer The timer may be started, or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. The timer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts incrementing in the up direction from zero. 12.2.
Timer_A Operation Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 12−2. The number of timer counts in the period is TACCR0+1. When the timer value equals TACCR0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TACCR0, the timer immediately restarts counting from zero. Figure 12−2.
Timer_A Operation Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 12−4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. Figure 12−4. Continuous Mode 0FFFFh 0h The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 12−5 shows the flag set cycle. Figure 12−5.
Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine. Figure 12−6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. In this usage, the time interval is controlled by hardware, not software, without impact from interrupt latency.
Timer_A Operation Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 12−7. The period is twice the value in TACCR0. Figure 12−7. Up/Down Mode 0FFFFh TACCR0 0h The count direction is latched.
Timer_A Operation Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The new period takes affect after the counter counts down to zero. When the timer is counting in the up direction, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down.
Timer_A Operation 12.2.4 Capture/Compare Blocks Three or five identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits.
Timer_A Operation Figure 12−11.Capture Cycle Idle Capture No Capture Taken Capture Read Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken COV = 1 Idle Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges.
Timer_A Operation 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12−2. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0.
Timer_A Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 12−12 using TACCR0 and TACCR1. Figure 12−12.
Timer_A Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 12−13 using TACCR0 and TACCR1. Figure 12−13.
Timer_A Operation Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 12−14 using TACCR0 and TACCR2. Figure 12−14.
Timer_A Operation 12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: - TACCR0 interrupt vector for TACCR0 CCIFG - TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register. In compare mode, any CCIFG flag is set if TAR counts to the associated TACCRx value. Software may also set or clear any CCIFG flag.
Timer_A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
Timer_A Registers 12.3 Timer_A Registers The Timer_A registers are listed in Table 12−3 and Table 12−4. Table 12−3.
Timer_A Registers TACTL, Timer_A Control Register 15 14 13 12 11 10 9 8 TASSELx Unused rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 Unused TACLR TAIE TAIFG rw−(0) w−(0) rw−(0) rw−(0) IDx rw−(0) MCx rw−(0) rw−(0) rw−(0) Unused Bits 15-10 Unused TASSELx Bits 9-8 Timer_A clock source select 00 TACLK 01 ACLK 10 SMCLK 11 Inverted TACLK IDx Bits 7-6 Input divider. These bits select the divider for the input clock.
Timer_A Registers TAR, Timer_A Register 15 14 13 12 11 10 9 8 TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 rw−(0) rw−(0) rw−(0) rw−(0) TARx rw−(0) TARx rw−(0) Bits 15-0 rw−(0) rw−(0) Timer_A register. The TAR register is the count of Timer_A.
Timer_A Registers TACCTLx, Capture/Compare Control Register 15 14 13 12 CCISx CMx 11 10 9 8 SCS SCCI Unused CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 CCIE CCI OUT COV CCIFG rw−(0) r rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) CMx Bit 15-14 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges CCISx Bit 13-12 Capture/compare input select.
Timer_A Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit. OUT Bit 2 Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high COV Bit 1 Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software.
Chapter 13 Timer_B Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_B. Timer_B3 (three capture/compare registers) is implemented in MSP430x43x devices. Timer_B7 (seven capture/compare registers) is implemented in MSP430x44x. Topic Page 13.1 Timer_B Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer_B Introduction 13.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_B Introduction Figure 13−1.
Timer_B Operation 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 13.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TBR may be cleared by setting the TBCLR bit.
Timer_B Operation 13.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0. The timer may then be restarted by loading a nonzero value to TBCL0. In this scenario, the timer starts incrementing in the up direction from zero. 13.2.
Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR(max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 13−2. The number of timer counts in the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TBCL0, the timer immediately restarts counting from zero. Figure 13−2.
Timer_B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR(max) and restarts from zero as shown in Figure 13−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 13−4. Continuous Mode TBR(max) 0h The TBIFG interrupt flag is set when the timer counts from TBR(max) to zero. Figure 13−5 shows the flag set cycle. Figure 13−5.
Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine. Figure 13−6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. The time interval is controlled by hardware, not software, without impact from interrupt latency.
Timer_B Operation Up/Down Mode The up/down mode is used if the timer period must be different from TBR(max) counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 13−7. The period is twice the value in TBCL0. Note: TBCL0 > TBR(max) If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It does not count down from TBR(max) to zero. Figure 13−7.
Timer_B Operation Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero.
Timer_B Operation 13.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits.
Timer_B Operation Figure 13−11.Capture Cycle Idle Capture No Capture Taken Capture Read Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Taken COV = 1 Idle Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges.
Timer_B Operation Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx. Compare data is written to each TBCCRx and automatically transferred to TBCLx. The timing of the transfer from TBCCRx to TBCLx is user-selectable with the CLLDx bits as described in Table 13−2. Table 13−2.
Timer_B Operation 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a high-impedance state. When the TBOUTH pin function is selected for the pin, and when the pin is pulled high, all Timer_B outputs are in a high-impedance state.
Timer_B Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 13−12 using TBCL0 and TBCL1. Figure 13−12.
Timer_B Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 13−13 using TBCL0 and TBCL1. Figure 13−13.
Timer_B Operation Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 13−14 using TBCL0 and TBCL3. Figure 13−14.
Timer_B Operation 13.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register. In compare mode, any CCIFG flag is set when TBR counts to the associated TBCLx value. Software may also set or clear any CCIFG flag.
Timer_B Operation TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
Timer_B Registers 13.3 Timer_B Registers The Timer_B registers are listed in Table 13−5. Table 13−5.
Timer_B Registers Timer_B Control Register TBCTL 15 14 13 12 TBCLGRPx Unused 11 CNTLx 10 9 Unused 8 TBSSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 Unused TBCLR TBIE TBIFG rw−(0) w−(0) rw−(0) rw−(0) IDx rw−(0) MCx rw−(0) rw−(0) rw−(0) Unused Bit 15 Unused TBCLGRP Bit 14-13 TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL
Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer_B interrupt flag.
Timer_B Registers TBCCTLx, Capture/Compare Control Register 15 14 13 12 CCISx CMx 11 10 SCS 9 CLLDx 8 CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 CCIE CCI OUT COV CCIFG rw−(0) r rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) CMx Bit 15-14 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges CCISx Bit 13-12 Capture/compare input select.
Timer_B Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit. OUT Bit 2 Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high COV Bit 1 Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software.
Timer_B Registers TBIV, Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 r0 r0 r0 r0 TBIVx Bits 15-0 TBIVx r−(0) 0 r−(0) r−(0) r0 Timer_B interrupt vector value TBIV Contents † Interrupt Source Interrupt Priority Interrupt Flag 00h No interrupt pending − 02h Capture/compare 1 TBCCR1 CCIFG 04h Capture/compare 2 TBCCR2 CCIFG 06h Capture/compare 3† TBCCR3 CCIFG 08h Capture/c
Chapter 14 The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1. Topic Page 14.1 USART Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . .
USART Introduction: UART Mode 14.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared.
USART Introduction: UART Mode Figure 14−1.
USART Operation: UART Mode 14.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency. 14.2.1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition.
USART Operation: UART Mode 14.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 14−3.
USART Operation: UART Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag. Any applicable error flag is also set. The user can then validate the received address.
USART Operation: UART Mode Address-Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 14−4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USART RXWAKE bit is set when a received character is a valid address character and is transferred to UxRXBUF.
USART Operation: UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) will be ignored. See the device-specific datasheet for parameters. When a low period on URXDx exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USART halts character reception and waits for the next low period on URXDx.
USART Operation: UART Mode 14.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 14−5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF, contains the character moved from the RX shift register after the character is received. Figure 14−5.
USART Operation: UART Mode 14.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins. This process is shown in Figure 14−6. When the UTXEx bit is reset the transmitter is stopped.
USART Operation: UART Mode 14.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 14−7. This combination supports fractional divisors for baud rate generation. The maximum USART baud rate is one-third the UART source clock frequency BRCLK. Figure 14−7. MSP430 Baud Rate Generator SSEL1 SSEL0 N = 215 28 ...
USART Operation: UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs.
USART Operation: UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced.
USART Operation: UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 14−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock. Figure 14−9.
USART Operation: UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7=0, m6=1, m5=1, m4=0, m3=1, m2=0, m1=1 and m0=1 The LSB of UxMCTL is used first.
USART Operation: UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 14−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. The transmit error is the accumulated timing error versus the ideal time of the bit period. Table 14−2.
USART Operation: UART Mode 14.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF.
USART Operation: UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served (when URXSE = 0) or when UxRXBUF is read. The operation is shown in Figure 14−11. Figure 14−11.
USART Operation: UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation. The ultra-fast turn-on of the DCO allows character reception after the start edge detection. When URXSE, URXIEx and GIE are set and a start edge occurs on URXDx, the internal signal URXS will be set.
USART Operation: UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) will be ignored by the USART and no interrupt request will be generated as shown in Figure 14−12. See the device-specific datasheet for parameters. Figure 14−12.
USART Registers: UART Mode 14.3 USART Registers: UART Mode Table 14−3 lists the registers for all devices implementing a USART module. Table 14−4 applies only to devices with a second USART module, USART1. Table 14−3.
USART Registers: UART Mode UxCTL, USART Control Register 7 6 5 4 3 2 1 0 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 PENA Bit 7 Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. PEV Bit 6 Parity select. PEV is not used when parity is disabled. 0 Odd parity 1 Even parity SPB Bit 5 Stop bit select.
USART Registers: UART Mode UxTCTL, USART Transmit Control Register 7 6 Unused CKPL rw−0 rw−0 5 4 SSELx rw−0 3 2 1 0 URXSE TXWAKE Unused TXEPT rw−0 rw−0 rw−0 rw−1 rw−0 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK SSELx Bits 5-4 Source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK URXSE Bit 3 UART receive start-edge. The bit enables the UART receive start-edge feature.
USART Registers: UART Mode UxRCTL, USART Receive Control Register 7 6 5 4 3 2 1 0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag. When PENA = 0, PE is read as 0. 0 No error 1 Character received with parity error OE Bit 5 Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read.
USART Registers: UART Mode UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw The valid baud-rate control range is 3 ≤ UxBR < 0FFFFh, where UxBR = {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR <3.
USART Registers: UART Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
USART Registers: UART Mode ME1, Module Enable Register 1 7 6 UTXE0 URXE0 rw−0 rw−0 5 4 3 2 1 0 UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0. 0 Module not enabled 1 Module enabled URXE0 Bit 6 USART0 receive enable. This bit enables the receiver for USART0. 0 Module not enabled 1 Module enabled Bits 5-0 These bits may be used by other modules. See device-specific datasheet.
USART Registers: UART Mode IE1, Interrupt Enable Register 1 7 6 UTXIE0 URXIE0 rw−0 rw−0 5 4 3 2 1 0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled Bits 5-0 These bits may be used by other modules. See device-specific datasheet.
USART Registers: UART Mode IFG1, Interrupt Flag Register 1 7 6 UTXIFG0 URXIFG0 rw−1 rw−0 5 4 3 2 1 0 UTXIFG0† Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending URXIFG0† Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending Bits 5-0 These bits may be used by other modules. See device-specific datasheet.
Chapter 15 USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1. Topic Page 15.1 USART Introduction: SPI Mode . . . . . . . . . . . . . .
USART Introduction: SPI Mode 15.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared.
USART Introduction: SPI Mode Figure 15−1.
USART Operation: SPI Mode 15.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: - SIMO Slave in, master out Master mode: SIMO is the data output line. Slave mode: SIMO is the data input line.
USART Operation: SPI Mode 15.2.2 Master Mode Figure 15−2. USART Master and External Slave MASTER Receive Buffer UxRXBUF SLAVE SIMO Transmit Buffer UxTXBUF Receive Shift Register MSB SIMO SPI Receive Buffer Px.x STE STE SS Port.x SOMI Transmit Shift Register LSB MSB LSB UCLK MSP430 USART SOMI Data Shift Register (DSR) LSB MSB SCLK COMMON SPI Figure 15−2 shows the USART as a master in both 3-pin and 4-pin configurations.
USART Operation: SPI Mode 15.2.3 Slave Mode Figure 15−3. USART Slave and External Master MASTER SIMO SPI Receive Buffer Transmit Buffer UxTXBUF Data Shift Register DSR MSB SLAVE SIMO Px.x STE STE SS Port.x SOMI SOMI LSB SCLK Receive Buffer UxRXBUF Transmit Shift Register Receive Shift Register MSB MSB LSB LSB UCLK COMMON SPI MSP430 USART Figure 15−3 shows the USART as a slave in both 3-pin and 4-pin configurations.
USART Operation: SPI Mode 15.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated. Transmit Enable When USPIEx = 0, any further write to UxTXBUF does not transmit.
USART Operation: SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 15−6 and Figure 15−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. Figure 15−6.
USART Operation: SPI Mode 15.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 15−8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are don’t care. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer. Figure 15−8.
USART Operation: SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 15−9. Figure 15−9.
USART Operation: SPI Mode 15.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF. UTXIFGx is set after a PUC or when SWRST = 1.
USART Operation: SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 15−11 and Figure 15−12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read. Figure 15−11.
USART Registers: SPI Mode 15.3 USART Registers: SPI Mode Table 15−1 lists the registers for all devices implementing a USART module. Table 15−2 applies only to devices with a second USART module, USART1. Table 15−1.
USART Registers: SPI Mode UxCTL, USART Control Register † 7 6 5 4 3 2 1 0 Unused Unused I2C† CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bits 7−6 Unused I2C† Bit 5 I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0 SPI mode 1 I2C mode CHAR Bit 4 Character length 0 7-bit data 1 8-bit data LISTEN Bit 3 Listen enable. The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled.
USART Registers: SPI Mode UxTCTL, USART Transmit Control Register 7 6 CKPH CKPL rw−0 rw−0 5 4 SSELx rw−0 rw−0 3 2 1 0 Unused Unused STC TXEPT rw−0 rw−0 rw−0 rw−1 CKPH Bit 7 Clock phase select. Controls the phase of UCLK. 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle CKPL Bit 6 Clock polarity select 0 The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK.
USART Registers: SPI Mode UxRCTL, USART Receive Control Register 7 6 5 4 3 2 1 0 FE Unused OE Unused Unused Unused Unused Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0 No conflict detected 1 A negative edge occurred on STE, indicating bus conflict Undefined Bit 6 Unused OE Bit 5 Overrun error flag.
USART Registers: SPI Mode UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2.
USART Registers: SPI Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
USART Registers: SPI Mode ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 USPIE0 rw−0 USPIE0 Bit 7 This bit may be used by other modules. See device-specific datasheet. Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0. 0 Module not enabled 1 Module enabled Bits 5-0 These bits may be used by other modules. See device-specific datasheet. ME2, Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 rw−0 USPIE1 Bits 7-5 These bits may be used by other modules.
USART Registers: SPI Mode IE1, Interrupt Enable Register 1 7 6 UTXIE0 URXIE0 rw−0 rw−0 5 4 3 2 1 0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled Bits 5-0 These bits may be used by other modules. See device-specific datasheet.
USART Registers: SPI Mode IFG1, Interrupt Flag Register 1 7 6 UTXIFG0 URXIFG0 rw−1 rw−0 5 4 3 2 1 0 UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending Bits 5-0 These bits may be used by other modules. See device-specific datasheet.
Chapter 16 OA The OA is a general purpose operational amplifier. This chapter describes the OA. Three OA modules are implemented in the MSP430FG43x devices. Topic Page 16.1 OA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 OA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3 OA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OA Introduction 16.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analogto-digital conversion. Features of the OA include: - Single supply, low-current operation - Rail-to-rail output - Software selectable Rail-to-Rail input - Programmable settling time vs. power consumption - Software selectable configurations - Software selectable feedback resistor ladder for PGA implementations Note: Multiple OA Modules Some devices may integrate more than one OA module.
OA Introduction Figure 16−1. OA Block Diagram OAPx=3 OAFCx=6 OANx=3 OAADC0 A12 ext. (OA0) A13 ext. (OA1) A14 ext. (OA2) 1 OAPx OAxI0 00 OA0I1 01 Int. DAC12_0OUT 10 Int. DAC12_1OUT 11 OAADC1 OAFCx=0 OAPMx 0 + 1 − 0 1 1 00 OAxI1 01 Int. DAC12_0OUT 10 Int. DAC12_1OUT 11 A1 int./ext., OA0O (OA0) A3 int./ext., OA1O (OA1) A5 int./ext., OA2O (OA2) 1 OAxOUT OAx OA1TAP (OA0) OA2TAP (OA1) OANx OA0TAP (OA2) OAxI0 A12 int. (OA0) A13 int. (OA1) A14 int.
OA 16.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. 16.2.1 OA Amplifier The OA is a configurable, low-current, rail-to-rail operational amplifier. It can be configured as an inverting amplifier, or a non-inverting amplifier, or can be combined with other OA modules to form differential amplifiers. The output slew rate of the OA can be configured for optimized settling time vs. power consumption with the OAPMx bits.
OA 16.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits. as listed in Table 16−1. Table 16−1.OA Mode Select OAFCx OA Mode 000 General-purpose opamp 001 Unity gain buffer 010 Reserved 011 Comparator 100 Non-inverting PGA amplifier 101 Reserved 110 Inverting PGA amplifier 111 Differential amplifier General Purpose Opamp Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAxCTL0 bits define the signal routing.
OA Non-Inverting PGA Mode In this mode the output of the OAx is connected to RTOP and RBOTTOM is connected to AVSS. The OAxTAP signal is connected to the inverting input of the OAx providing a non-inverting amplifier configuration with a programmable gain of [1+OAxTAP ratio]. The OAxTAP ratio is selected by the OAFBRx bits. If the OAFBRx bits = 0, the gain is unity. The non-inverting input is selected by the OAPx bits.
OA Figure 16−2 shows an example of a two-opamp differential amplifier using OA0 and OA1. The control register settings and are shown in Table 16−2. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 16−3. The OAx interconnections are shown in Figure 16−3. Table 16−2.Two-Opamp Differential Amplifier Control Register Settings Register Settings (binary) OA0CTL0 00 xx xx 0 0 OA0CTL1 000 111 0 x OA1CTL0 10 xx xx x x OA1CTL1 xxx 110 0 x Table 16−3.
OA Figure 16−3. Two Opamp Differential Amplifier OAx Interconnections OAADC0 A13 ext. OAPx 1 OAPMx 00 01 A13 int. 0 OAADC1 V2 0 10 + 1 11 1 A3 int./ext.
OA Figure 16−4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2. The control register settings are shown in Table 16−4. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal. The gain settings are shown in Table 16−5. The OAx interconnections are shown in Figure 16−5. Table 16−4.
OA Figure 16−5. Three Opamp Differential Amplifier OAx Interconnections OAPx OAADC0 OAPMx 00 01 A14 ext. 0 10 1 11 1 + OA0OUT OA0 OAPMx − OAADC1 0 11 1 4R 001 00 2R 10 2R 11 011 100 OAFBRx R 000 3 R 001 000 R 010 001 R 011 010 100 011 101 100 110 101 101 110 111 OA0RBOTTOM OAADC1 01 010 4R 4R 2R 2R OAPx OAPMx 00 11 0 000 OA0TAP 10 A5 int./ext., OA2O − OA0TAP 4R 01 1 OA2 3 01 10 + 1 OAFBRx 00 A14 int.
OA Registers 16.3 OA Registers The OA registers are listed in Table 16−6. Table 16−6.
OA Registers OAxCTL0, Opamp Control Register 0 7 6 5 OANx rw−0 4 3 OAPx rw−0 rw−0 2 OAPMx rw−0 rw−0 rw−0 1 0 OAADC1 OAADC0 rw−0 rw−0 OANx Bits 7-6 Inverting input select. These bits select the input signal for the OA inverting input. 00 OAxI0 01 OAxI1 10 DAC0 internal 11 DAC1 internal OAPx Bits 5-4 Non-inverting input select. These bits select the input signal for the OA non-inverting input.
OA Registers OAxCTL1, Opamp Control Register 1 7 6 5 4 OAFBRx rw−0 rw−0 3 2 OAFCx rw−0 rw−0 rw−0 rw−0 1 0 Reserved OARRIP rw−0 rw−0 OAFBRx Bits 7-5 OAx feedback resistor select 000 Tap 0 001 Tap 1 010 Tap 2 011 Tap 3 100 Tap 4 101 Tap 5 110 Tap 6 111 Tap 7 OAFCx Bits 4-2 OAx function control.
Chapter 17 Comparator_A Comparator_A is an analog voltage comparator. This chapter describes Comparator_A. Comparator_A is implemented in all MSP430x4xx devices. Topic Page 17.1 Comparator_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 Comparator_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 Comparator_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator_A Introduction 17.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.
Comparator_A Introduction Figure 17−1. Comparator_A Block Diagram VCC 0V P2CA0 CAEX 1 0 CAON 0 CA0 1 1 0 CA1 CAF 0 CCI1B ++ 0 0 −− 1 1 CAOUT 0 1 1 Set_CAIFG Tau ~ 2.0ms P2CA1 0V 1 0 CAREFx CARSEL 0.5x VCC 00 0 1 VCAREF 01 10 0.
Comparator_A Operation 17.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 17.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the – terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON.
Comparator_A Operation 17.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figure 17−2.
Comparator_A Operation 17.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption.
Comparator_A Operation 17.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 17−5. A reference resister Rref is compared to Rmeas. Figure 17−5. Temperature Measurement System Rref Px.x Rmeas Px.
Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 17−6. Figure 17−6. Timing for Temperature Measurement Systems VC VCC Rmeas Rref 0.
Comparator_A Registers 17.3 Comparator_A Registers The Comparator_A registers are listed in Table 17−1. Table 17−1.
Comparator_A Registers CACTL1, Comparator_A Control Register 1 7 6 CAEX CARSEL rw−(0) rw−(0) 5 4 CAREFx rw−(0) rw−(0) 3 2 1 0 CAON CAIES CAIE CAIFG rw−(0) rw−(0) rw−(0) rw−(0) CAEX Bit 7 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. CARSEL Bit 6 Comparator_A reference select. This bit selects which terminal the VCAREF is applied to.
Comparator_A Registers CACTL2, Comparator_A Control Register 2 7 6 5 4 Unused rw−(0) rw−(0) rw−(0) rw−(0) 3 2 1 0 P2CA1 P2CA0 CAF CAOUT rw−(0) rw−(0) rw−(0) r−(0) Unused Bits 7-4 Unused. P2CA1 Bit 3 Pin to CA1. This bit selects the CA1 pin function. 0 The pin is not connected to CA1 1 The pin is connected to CA1 P2CA0 Bit 2 Pin to CA0. This bit selects the CA0 pin function.
Chapter 18 LCD Controller The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes LCD controller. The LCD controller is implemented on all MSP430x4xx devices, except the MSP430x42x0 devices. Topic Page 18.1 LCD Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18−2 18.2 LCD Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18−4 18.3 LCD Controller Registers . . . . . . . . . . . . . . . . .
LCD Controller Introduction 18.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs.
LCD Controller Introduction Figure 18−1.
LCD Controller Operation 18.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operation of LCD controller is discussed in the following sections. 18.2.1 LCD Memory The LCD memory map is shown in Figure 18−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode. To turn on an LCD segment, its corresponding memory bit is set. Figure 18−2.
LCD Controller Operation 18.2.4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33, R23, R13, and R03. Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in Table 18−1. The resistor value R is typically 680 kW. Values of R from 100kW to 1MW can be used depending on LCD requirements. R33 is a switched-VCC output.
LCD Controller Operation 18.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 18−3 shows some example static waveforms. Figure 18−3. Example Static Waveforms V1 COM0 V5 fframe V1 SP1 COM0 V1 SP2 SP1 SP6 V5 a V5 V1 SP2 b SP7 SP3 Resulting Voltage for Segment a (COM0−SP1) Segment Is On. 0V V1 SP5 SP8 SP4 SP = Segment Pin 18-6 LCD Controller Resulting Voltage for Segment b (COM0−SP2) Segment Is Off.
LCD Controller Operation Figure 18−4 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−4.
LCD Controller Operation Static Mode Software Example ; ; ; a b c d e f g h ; : ; All eight segments of a digit are often located in four display memory bytes with the static display method. EQU 001h EQU 010h EQU 002h EQU 020h EQU 004h EQU 040h EQU 008h EQU 080h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table (Rx),RY ; Load segment information ; into temporary memory. ; (Ry) = 0000 0000 hfdb geca MOV.
LCD Controller Operation 18.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 18−5 shows some example 2-mux waveforms. Figure 18−5. Example 2-Mux Waveforms COM1 COM0 fframe COM1 COM0 V1 V3 V5 V1 V3 V5 V1 SP1 V5 SP2 V1 b V5 h V1 V3 0V −V3 −V1 SP1 SP4 SP2 Resulting Voltage for Segment h (COM0−SP2) Segment Is On. SP3 SP = Segment Pin Resulting Voltage for Segment b (COM1−SP2) Segment Is Off.
LCD Controller Operation Figure 18−6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−6.
LCD Controller Operation 2-Mux Mode Software Example ; ; ; a b c d e f g h ; ; ; ; All eight segments of a digit are often located in two display memory bytes with the 2mux display rate EQU 002h EQU 020h EQU 008h EQU 004h EQU 040h EQU 001h EQU 080h EQU 010h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. ........... ........... MOV.B Table(Rx),Ry ; ; MOV.B Ry,&LCDn ; ; ; ; RRA Ry ; RRA Ry ; MOV.B Ry,&LCDn+1 ; ; ........... ...........
LCD Controller Operation 18.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 18−7 shows some example 3-mux waveforms. Figure 18−7. Example 3-Mux Waveforms COM2 COM0 fframe COM1 COM1 COM0 COM2 SP1 e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 d SP2 SP3 SP1 V1 V2 V4 V5 SP2 SP = Segment Pin SP3 Resulting Voltage for Segment e (COM0−SP1) Segment Is Off.
LCD Controller Operation Figure 18−8 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−8.
LCD Controller Operation 3-Mux Mode Software Example ; The 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ; a EQU 0040h b EQU 0400h c EQU 0200h d EQU 0010h e EQU 0001h f EQU 0002h g EQU 0020h h EQU 0100h Y EQU 0004h ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; LSDigit of register of Rx.
LCD Controller Operation 18.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 18−9 shows some example 4-mux waveforms. Figure 18−9. Example 4-Mux Waveforms COM3 COM0 COM2 COM1 fframe COM1 V1 V2 V4 V5 COM2 V1 V2 V4 V5 COM0 COM3 e V1 V2 V4 V5 V1 V2 V4 V5 SP1 V1 V2 V4 V5 SP2 V1 V2 V4 V5 c SP2 SP1 SP = Segment Pin V1 Resulting Voltage for Segment e (COM1−SP1) Segment Is Off.
LCD Controller Operation Figure 18−10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−10.
LCD Controller Operation 4-Mux Mode Software Example ; ; ; a b c d e f g h ; ; ; ; ; The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte EQU 080h EQU 040h EQU 020h EQU 001h EQU 002h EQU 008h EQU 004h EQU 010h The LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table(Rx),&LCDn ; ; ; ; ........... ........... Table DB a+b+c+d+e+f DB b+c ........... .......
LCD Controller Operation 18.3 LCD Controller Registers The LCD Controller registers are listed in Table 18−2. Table 18−2.
LCD Controller Operation LCDCTL, LCD Control Register 7 6 5 4 LCDPx rw−0 rw−0 3 LCDMXx rw−0 rw−0 rw−0 2 1 0 LCDSON Unused LCDON rw−0 rw−0 rw−0 LCDPx Bits 7-5 LCD Port Select. These bits select the pin function to be port I/O or LCD function for groups of segments pins. These bits ONLY affect pins with multiplexed functions. Dedicated LCD pins are always LCD function.
Chapter 19 LCD_A Controller The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_A controller. The LCD_A controller is implemented on the MSP430x42x0 and MSP430F46xx devices. Topic Page 19.1 LCD Controller Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19−2 19.2 LCD Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19−4 19.3 LCD Controller Registers . . . . . . . . . . . . . . . . . . .
LCD_A Controller Introduction 19.1 LCD_A Controller Introduction The LCD_A controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs.
LCD_A Controller Introduction Figure 19−1. LCD_A Controller Block Diagram SEG39 0A4h Mux S39 SEG38 Mux S38 Segment Output Control Display Memory 20x 8−bits SEG1 Mux S1 SEG0 091h Mux S0 10 COM3 LCDSx LCDSON Common Output Control COM2 COM1 COM0 LCDFREQx Divider /32 ..
LCD_A Controller Operation 19.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup and operation of the LCD_A controller is discussed in the following sections. 19.2.1 LCD Memory The LCD memory map is shown in Figure 19−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode. To turn on an LCD segment, its corresponding memory bit is set. Figure 19−2.
LCD_A Controller Operation 19.2.3 LCD_A Voltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveform voltage, V1, as well as the fractional LCD biasing voltages V2 − V5. VLCD may be sourced from AVCC, an internal charge pump, or externally. All internal voltage generation is disabled if the oscillator sourcing ACLK is turned off (OSCOFF = 1) or the LCD_A module is disabled (LCDON = 0).
LCD_A Controller Operation To source the bias voltages V2 − V4 externally, REXT is set. This also disables the internal bias generation. Typically an equally weighted resistor divider is used with resistors ranging from 100 k to 1 M When using an external resistor divider, the VLCD voltage may be sourced from the internal charge pump when VLCDEXT = 0. V5 can also be sourced externally when R03EXT is set. When using an external resistor divider R33 may serve as a switched-VLCD output when VLCDEXT = 0.
LCD_A Controller Operation The internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3 bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In static mode the internal divider is disabled. Some devices share the LCDCAP, R33, and R23 functions. In this case, the charge pump cannot be used together with an external resistor divider with 1/3 biasing. When R03 is not available externally. The V5 is always AVSS.
LCD_A Controller Operation 19.2.4 LCD Timing Generation The LCD_A controller uses the fLCD signal from the integrated ACLK prescaler to generate the timing for common and segment lines. ACLK is assumed to be 32768 Hz for generating fLCD. The fLCD frequency is selected with the LCDFREQx bits.
LCD_A Controller Operation 19.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 19−4 shows some example static waveforms. Figure 19−4. Example Static Waveforms V1 COM0 V5 fframe V1 SP1 V5 COM0 SP6 V1 V5 SP2 SP1 a V1 SP2 b SP7 SP3 Resulting Voltage for Segment a (COM0−SP1) Segment Is On. 0V V1 SP5 SP8 SP4 SP = Segment Pin Resulting Voltage for Segment b (COM0−SP2) Segment Is Off.
LCD_A Controller Operation Figure 19−5 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−5.
LCD_A Controller Operation Static Mode Software Example ; ; ; a b c d e f g h ; : ; All eight segments of a digit are often located in four display memory bytes with the static display method. EQU 001h EQU 010h EQU 002h EQU 020h EQU 004h EQU 040h EQU 008h EQU 080h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table (Rx),RY ; Load segment information ; into temporary memory. ; (Ry) = 0000 0000 hfdb geca MOV.
LCD_A Controller Operation 19.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 19−6 shows some example 2-mux, 1/2 bias waveforms. Figure 19−6. Example 2-Mux Waveforms COM1 COM0 fframe COM1 COM0 V1 V3 V5 V1 V3 V5 V1 SP1 V5 SP2 V1 b V5 h V1 V3 0V −V3 −V1 SP1 SP4 SP2 Resulting Voltage for Segment h (COM0−SP2) Segment Is On. SP3 SP = Segment Pin Resulting Voltage for Segment b (COM1−SP2) Segment Is Off.
LCD_A Controller Operation Figure 19−7 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−7.
LCD_A Controller Operation 2-Mux Mode Software Example ; ; ; a b c d e f g h ; ; ; ; All eight segments of a digit are often located in two display memory bytes with the 2mux display rate EQU 002h EQU 020h EQU 008h EQU 004h EQU 040h EQU 001h EQU 080h EQU 010h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. ........... ........... MOV.B Table(Rx),Ry ; ; MOV.B Ry,&LCDn ; ; ; ; RRA Ry ; RRA Ry ; MOV.B Ry,&LCDn+1 ; ; ........... .........
LCD_A Controller Operation 19.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 19−8 shows some example 3-mux, 1/3 bias waveforms. Figure 19−8. Example 3-Mux Waveforms COM2 COM0 fframe COM1 COM1 COM0 COM2 SP1 e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 d SP2 V5 SP3 SP1 V1 V2 V4 V5 SP2 SP = Segment Pin V1 SP3 V5 V1 Resulting Voltage for Segment e (COM0−SP1) Segment Is Off.
LCD_A Controller Operation Figure 19−9 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−9.
LCD_A Controller Operation 3-Mux Mode Software Example ; The 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ; a EQU 0040h b EQU 0400h c EQU 0200h d EQU 0010h e EQU 0001h f EQU 0002h g EQU 0020h h EQU 0100h Y EQU 0004h ; The LSDigit of register Rx should be displayed. ; The Table represents the ’on’−segments according to the ; LSDigit of register of Rx.
LCD_A Controller Operation 19.2.9 4-Mux Mode In 3-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 19−10 shows some example 4-mux, 1/3 bias waveforms. Figure 19−10. Example 4-Mux Waveforms COM3 COM0 COM2 COM1 fframe COM1 V1 V2 V4 V5 COM2 V1 V2 V4 V5 COM0 COM3 e V1 V2 V4 V5 V1 V2 V4 V5 SP1 V1 V2 V4 V5 SP2 V1 V2 V4 V5 c SP2 SP1 SP = Segment Pin V1 Resulting Voltage for Segment e (COM1−SP1) Segment Is Off.
LCD_A Controller Operation Figure 19−11 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−11.
LCD_A Controller Operation 4-Mux Mode Software Example ; ; ; a b c d e f g h ; ; ; ; ; The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte EQU 080h EQU 040h EQU 020h EQU 001h EQU 002h EQU 008h EQU 004h EQU 010h The LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table(Rx),&LCDn ; ; ; ; ........... ........... Table DB a+b+c+d+e+f DB b+c ........... .....
LCD_A Controller Operation 19.3 LCD Controller Registers The LCD Controller registers are listed in Table 19−2. Table 19−2.
LCD_A Controller Operation LCDACTL, LCD_A Control Register 7 6 5 4 LCDFREQx rw−0 rw−0 3 LCDMXx rw−0 rw−0 rw−0 2 1 0 LCDSON Unused LCDON rw−0 rw−0 rw−0 LCDFREQx Bits 7-5 LCD Frequency Select. These bits select the ACLK divider for the LCD frequency. 000 Divide by 32 001 Divide by 64 010 Divide by 96 011 Divide by 128 100 Divide by 192 101 Divide by 256 110 Divide by 384 111 Divide by 512 LCDMXx Bits 4-3 LCD mux rate. These bits select the LCD mode.
LCD_A Controller Operation LCDAPCTL0, LCD_A Port Control Register 0 7 6 5 4 3 2 1 0 LCDS28 LCDS24 LCDS20 LCDS16 LCDS12 LCDS8 LCDS4 LCDS0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDS28 Bit 7 LCD Segment 28 to 31 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCDS24 Bit 6 LCD Segment 24 to 27 Enable. This bit only affects pins with multiplexed functions.
LCD_A Controller Operation LCDAPCTL1, LCD_A Port Control Register 1 7 6 5 4 3 2 Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 1 0 LCDS36 LCDS32 rw−0 rw−0 Unused Bits 7−2 Unused LCDS36 Bit 1 LCD Segment 36 to 39 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0 Multiplexed pins are port functions. 1 Pins are LCD functions LCDS32 Bit 0 LCD Segment 32 to 35 Enable. This bit only affects pins with multiplexed functions.
LCD_A Controller Operation LCDAVCTL0, LCD_A Voltage Control Register 0 7 6 5 4 3 Unused R03EXT REXT VLCDEXT LCDCPEN rw−0 rw−0 rw−0 rw−0 rw−0 2 1 VLCDREFx rw−0 rw−0 0 LCD2B rw−0 Unused Bit 7 Unused R03EXT Bit 6 V5 voltage select. This bit selects the external connection for the lowest LCD voltage. R03EXT is ignored if there is no R03 pin available. 0 V5 is AVCC 1 V5 is sourced from the R03 pin REXT Bit 5 V2 − V4 voltage select.
LCD_A Controller Operation LCDAVCTL1, LCD_A Voltage Control Register 1 7 6 5 4 3 Unused rw−0 2 1 VLCDx rw−0 rw−0 rw−0 rw−0 0 Unused rw−0 rw−0 rw−0 Unused Bits 7−5 Unused VLCDx Bits 4−1 Charge pump voltage select. LCDCPEN must be 1 for the charge pump to be enabled. AVCC is used for VLCD when VLCDx = 0000 and VREFx = 00 and VLCDEXT = 0. 0000 Charge pump disabled. 0001 VLCD = 2.60V 0010 VLCD = 2.66V 0011 VLCD = 2.72V 0100 VLCD = 2.78V 0101 VLCD = 2.84V 0110 VLCD = 2.90V 0111 VLCD = 2.
Chapter 20 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter. This chapter describes the ADC12. The ADC12 is implemented in the MSP430x43x and MSP430x44x devices. Topic Page 20.1 ADC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.2 ADC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3 ADC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC12 Introduction 20.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
ADC12 Introduction Figure 20−1. ADC12 Block Diagram REFON INCHx=0Ah REF2_5V Ve REF+ on 1.5 V or 2.5 V Reference VREF+ VREF− / Ve REF− AVCC INCHx AVSS 4 A0 A1 A2 A3 A4 A5 A6 A7 A12† A13† A14† A15† 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SREF2 1 Ref_x SREF1 SREF0 11 10 01 00 0 AVCC ADC12OSC ADC12SSELx ADC12ON ADC12DIVx VR− Sample and Hold VR+ 00 Divider /1 ..
ADC12 Operation 20.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 20.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory. The core uses two programmable/selectable voltage levels (VR+ and VR−) to define the upper and lower limits of the conversion.
ADC12 Operation 20.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 20−2. The input multiplexer is also a T-switch to minimize the coupling between channels.
ADC12 Operation 20.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin VREF+. Setting REFON=1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0. The reference can be turned off to save power when not in use.
ADC12 Operation 20.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: - The ADC12SC bit The Timer_A Output Unit 1 The Timer_B Output Unit 0 The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit. The SAMPCON signal controls the sample period and start of conversion. When SAMPCON is high, sampling is active.
ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period tsample. The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample. The total sampling time is tsample plus tsync. See Figure 20−4. The SHTx bits select the sampling time in 4x multiples of ADC12CLK.
ADC12 Operation Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown below in Figure 20−5. An internal MUX-on input resistance RI (max. 2 kΩ) in series with capacitor CI (max. 40 pF) is seen by the source. The capacitor CI voltage VC must be charged to within 1/2 LSB of the source voltage VS for an accurate 12-bit conversion. Figure 20−5.
ADC12 Operation 20.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used. A sequence rolls over from ADC12MEM15 to ADC12MEM0 when the EOS bit in ADC12MCTL15 is not set.
ADC12 Operation Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 20−6 shows the flow of the Single-Channel, Single-Conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each conversion. Figure 20−6.
ADC12 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 20−7 shows the sequence-of-channels mode. When ADC12SC triggers a sequence, successive sequences can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each sequence.
ADC12 Operation Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 20−8 shows repeat-single-channel mode Figure 20−8.
ADC12 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re-starts the sequence. Figure 20−9 shows the repeat-sequence-of-channels mode. Figure 20−9.
ADC12 Operation Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed.
ADC12 Operation 20.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc. The typical temperature sensor transfer function is shown in Figure 20−10. When using the temperature sensor, the sample period must be greater than 30 µs.
ADC12 Operation 20.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry.
ADC12 Operation 20.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV, ADC12MEMx overflow - ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read.
ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
ADC12 Registers 20.3 ADC12 Registers The ADC12 registers are listed in Table 20−2 . Table 20−2.
ADC12 Registers ADC12CTL0, ADC12 Control Register 0 15 14 13 12 11 10 SHT1x 9 8 SHT0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 MSC REF2_5V REFON ADC12ON ADC12OVIE ADC12 TOVIE ENC ADC12SC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 SHT1x Bits 15-12 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15.
ADC12 Registers MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed. REF2_5V Bit 6 Reference generator voltage. REFON must also be set. 0 1.5 V 1 2.
ADC12 Registers ADC12CTL1, ADC12 Control Register 1 15 14 13 12 11 CSTARTADDx 10 SHSx 9 8 SHP ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12DIVx rw−(0) rw−(0) ADC12SSELx rw−(0) rw−(0) rw−(0) ADC12 BUSY CONSEQx rw−(0) rw−(0) r−(0) Modifiable only when ENC = 0 CSTART ADDx Bits 15-12 Conversion start address.
ADC12 Registers ADC12 SSELx Bits 4-3 ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits 2-1 Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12 BUSY Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active.
ADC12 Registers ADC12MCTLx, ADC12 Conversion Memory Control Registers 7 6 EOS rw−(0) 5 4 3 2 SREFx rw−(0) rw−(0) 1 0 rw−(0) rw−(0) INCHx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.
ADC12 Registers ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12IEx Bits 15-0 Interrupt enable.
ADC12 Registers ADC12IV, ADC12 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 r0 r0 ADC12IVx Bits 15-0 ADC12IVx r−(0) r−(0) r−(0) 0 r−(0) r−(0) r0 ADC12 interrupt vector value ADC12IV Contents Interrupt Source Interrupt Flag 000h No interrupt pending − 002h ADC12MEMx overflow − 004h Conversion time overflow − 006h ADC12MEM0 interrupt flag ADC12IFG0 008h ADC12MEM1 interrupt flag ADC12IF
Chapter 21 SD16 The SD16 module is a multichannel 16-bit, sigma-delta analog-to-digital converter. This chapter describes the SD16. The SD16 module is implemented in the MSP430FE42x and MSP430F42x devices. Topic Page 21.1 SD16 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 SD16 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.3 SD16 Registers . . . . . . . . . . . . . . . . . . . .
SD16 Introduction 21.1 SD16 Introduction The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully differential multiplexed inputs including a built-in temperature sensor. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 256.
SD16 Introduction Figure 21−1. SD16 Block Diagram SD16 Control Block SD16REFON Reference 1.2V VREF AV CC AV SS SD16SSELx SD16DIVx Divider 1/2/4/8 00 MCLK 01 SMCLK 10 ACLK 11 TACLK SD16VMIDON Temperature sensor Reference fM Channel 0 Reference Temperature sensor fM Group/Start Conversion Logic SD16INCHx A1.0 A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.
SD16 Operation 21.2 SD16 Operation The SD16 module is configured with user software. The setup and operation of the SD16 is discussed in the following sections. 21.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 21.2.
SD16 Operation 21.2.5 Channel Selection Each SD16 channel can convert up to 8 differential pair inputs multiplexed into the PGA. Up to six input pairs (A0-A5) are available externally on the device. See the device-specific data sheet for analog input pin information. An internal temperature sensor is available to each channel using the A6 multiplexer input. Input A7 is a shorted connection between the + and - input pair and can be used to calibrate the offset of each SD16 input stage.
SD16 Operation 21.2.6 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC3 comb filter. The transfer function is described in the z-Domain by: H(z) + 1 ǒOSR 1 * z *OSR 1 * z *1 Ǔ 3 and in the frequency domain by: ȱsincǒOSRp Ǔȳ ȡ 1 Hǒ f Ǔ +ȧ ȧ +ȧOSR ǒ Ǔ sinc p Ȳ ȴ Ȣ f 3 fM f fM ǒ sin OSR ǒ sin p fM f fM 3 Ǔȣ ȧ ĂǓ Ȥ f p Ă where the oversampling rate, OSR, is the ratio of the modulator frequency fM to the sample frequency fS.
SD16 Operation Figure 21−3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input. If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion.
SD16 Operation Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits. Figure 21−4 shows the digital filter output bits and their relation to SD16MEMx for each OSR. For example, for OSR = 256 and LSBACC = 1, the SD16MEMx register contains bits 23 − 8 of the digital filter output. When OSR = 32, the SD16MEMx LSB is always zero.
SD16 Operation 21.2.7 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversion results for each channel are moved to the corresponding SD16MEMx register with each decimation step of the digital filter. The SD16IFG bit for a given channel is set when new data is written to SD16MEMx. SD16IFG is automatically cleared when SD16MEMx is read by the CPU or may be cleared with software.
SD16 Operation 21.2.8 Conversion Modes The SD16 module can be configured for four modes of operation, listed in Table 21−2. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode. Table 21−2.Conversion Mode Summary SD16SNGL SD16GRP{ † Mode Operation 1 0 Single channel, Single conversion A single channel is converted once. 0 0 Single channel, Continuous conversion A single channel is converted continuously.
SD16 Operation Figure 21−6.
SD16 Operation Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set. SD16SC bits for all grouped channels will be automatically set and cleared with the master channel’s SD16SC bit. SD16SC for each channel in the group can also be cleared in software independently.
SD16 Operation 21.2.9 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of fM clock cycles and can range from 0 to 255. Figure 21−8 shows an example using SD16PREx. Figure 21−8.
SD16 Operation Figure 21−9. Start of Conversion using Preload SD16OSRx = 32 f M cycles: 40 SD16PRE0 = 8 Delayed Conversion 32 32 Conversion Conversion 1st Sample Ch0 SD16PRE1 = 0 32 32 32 Conversion Conversion Conversion Conversion 1st Sample Ch1 Start of Conversion Time When channels are grouped, care must be taken when a channel or channels operate in single conversion mode or are disabled in software while the master channel remains active.
SD16 Operation 21.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel SD16INCHx = 110. Any other configuration is done as if an external channel was selected, including SD16INTDLYx and SD16GAINx settings. The typical temperature sensor transfer function is shown in Figure 21−11.
SD16 Operation 21.2.11 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16 overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read.
SD16 Operation SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
SD16 Registers 21.3 SD16 Registers The SD16 registers are listed in Table 21−3: Table 21−3.
SD16 Registers SD16CTL, SD16 Control Register 15 14 13 12 11 10 9 8 Reserved SD16LP r0 r0 r0 r0 r0 r0 r0 rw−0 7 6 5 4 3 2 1 0 SD16 VMIDON SD16 REFON SD16OVIE Reserved rw−0 rw−0 rw−0 r0 SD16DIVx rw−0 rw−0 SD16SSELx rw−0 rw−0 Reserved Bits 15-9 Reserved SD16LP Bit 8 Low power mode. This bit selects a reduced speed, reduced power mode for the SD16. 0 Low-power mode is disabled 1 Low-power mode is enabled. The maximum clock frequency for the SD16 is reduced.
SD16 Registers SD16CCTLx, SD16 Channel x Control Register 15 14 13 12 11 Reserved 10 9 SD16SNGL 8 SD16OSRx r0 r0 r0 r0 r0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 SD16 LSBTOG SD16 LSBACC SD16 OVIFG SD16DF SD16IE SD16IFG SD16SC SD16GRP rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r(w)−0 Reserved Bits 15-11 Reserved SD16SNGL Bit 10 Single conversion mode select 0 Continuous conversion mode 1 Single conversion mode SD16OSRx Bits 9-8 Oversampling ratio 00 256 01 128 10 64 11 32 S
SD16 Registers SD16IFG Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software. 0 No interrupt pending 1 Interrupt pending SD16SC Bit 1 SD16 start conversion 0 No conversion start 1 Start conversion SD16GRP Bit 0 SD16 group. Groups SD16 channel with next higher channel. Not used for the last channel.
SD16 Registers SD16MEMx, SD16 Channel x Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 r r r Conversion Results r r Conversion Result Bits 15-0 r r r Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit.
SD16 Registers SD16IV, SD16 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 r0 r0 r0 SD16IVx Bits 15-0 SD16IVx r−0 r−0 0 r−0 r−0 r0 SD16 interrupt vector value SD16IV Contents Interrupt Source Interrupt Flag 000h No interrupt pending − 002h SD16MEMx overflow SD16CCTLx SD16OVIFG† 004h SD16_0 Interrupt SD16CCTL0 SD16IFG 006h SD16_1 Interrupt SD16CCTL1 SD16IFG 008h SD16_2 Interrupt SD16
Chapter 22 SD16_A The SD16_A module is a single-converter 16-bit, sigma-delta analog-to-digital conversion module with high impedance input buffer. This chapter describes the SD16_A. The SD16_A module is implemented in the MSP430F42x0 devices. Topic Page 22.1 SD16_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 SD16_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.3 SD16_A Registers . . .
SD16_A Introduction 22.1 SD16_A Introduction The SD16_A module consists of one sigma-delta analog-to-digital converter with an high impedance input buffer and an internal voltage reference. It has up to 8 fully differential multiplexed inputs including a built-in temperature sensor. The converter is based on a second-order oversampling sigma-delta modulator and digital decimation filter. The decimation filter is a comb type filter with selectable oversampling ratios of up to 1024.
SD16_A Introduction Figure 22−1. SD16_A Block Diagram SD16REFON 0 VREF Reference 1.2V AV CC SD16SSELx SD16XDIVx SD16DIVx 1 AV SS Reference fM Divider 1/3/16/48 Divider 1/2/4/8 00 MCLK 01 SMCLK 10 ACLK 11 TACLK SD16VMIDON Start Conversion Logic SD16INCHx A0 A1 A2 A3 A4 A5 A6 A7 + − + − + − + − + − + − + − + − SD16SC SD16SNGL 000 001 SD16BUFx SD16GAINx SD16OSRx 010 15 011 100 BUF 2ndOrder Σ∆ Modulator PGA 1..
SD16_A Operation 22.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 22.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 22.2.
SD16_A Operation 22.2.5 Channel Selection The SD16_A can convert up to 8 differential pair inputs multiplexed into the PGA. Up to five input pairs (A0-A4) are available externally on the device. A resistive divider to measure the supply voltage is available using the A5 multiplexer input. An internal temperature sensor is available using the A6 multiplexer input. Input A7 is a shorted connection between the + and - input pair and can be used to calibrate the offset of the SD16_A input stage.
SD16_A Operation 22.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC3 comb filter. The transfer function is described in the z-Domain by: H(z) + 1 ǒOSR 1 * z *OSR 1 * z *1 Ǔ 3 and in the frequency domain by: ȱsincǒOSRp Ǔȳ ȡ 1 Hǒ f Ǔ +ȧ ȧ +ȧOSR ǒ Ǔ sinc p Ȳ ȴ Ȣ f 3 fM f fM ǒ sin OSR ǒ sin p fM f fM 3 Ǔȣ ȧ ĂǓ Ȥ f p Ă where the oversampling rate, OSR, is the ratio of the modulator frequency fM to the sample frequency fS.
SD16_A Operation Figure 22−3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input. If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion.
SD16_A Operation Digital Filter Output The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 22−4 shows the digital filter output and their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNI setting. For example, for OSR = 1024, LSBACC = 1, and SD16UNI = 1, the SD16MEM0 register contains bits 28 − 13 of the digital filter output. When OSR = 32, the one (SD16UNI = 0) or two (SD16UNI=1) LSBs are always zero.
SD16_A Operation OSR=256, LSBACC=1, SD16UNI=1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR=256, LSBACC=0, SD16UNI=1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 OSR=256, LSBACC=1, SD16UNI=0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OSR=256, LSBACC=0, SD16UNI=0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
SD16_A Operation 22.2.8 Conversion Memory Register: SD16MEM0 The SD16MEM0 register is associated with the SD16_A channel. Conversion results are moved to the SD16MEM0 register with each decimation step of the digital filter. The SD16IFG bit is set when new data is written to SD16MEM0. SD16IFG is automatically cleared when SD16MEM0 is read by the CPU or may be cleared with software.
SD16_A Operation 22.2.9 Conversion Modes The SD16_A module can be configured for two modes of operation, listed in Table 22−3. The SD16SNGL bit selects the conversion mode. Table 22−3.Conversion Mode Summary SD16SNGL Mode Operation 1 Single conversion The channel is converted once. 0 Continuous conversion The channel is converted continuously. Single Conversion Setting the SD16SC bit of the channel initiates one conversion on that channel when SD16SNGL = 1.
SD16_A Operation 22.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel SD16INCHx = 110. Any other configuration is done as if an external channel was selected, including SD16INTDLYx and SD16GAINx settings. The typical temperature sensor transfer function is shown in Figure 22−7.
SD16_A Operation 22.2.11 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bit is set when the SD16MEM0 memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16_A overflow condition occurs when a conversion result is written to SD16MEM0 location before the previous conversion result was read.
SD16_A Registers 22.3 SD16_A Registers The SD16_A registers are listed in Table 22−4: Table 22−4.
SD16_A Registers SD16CTL, SD16_A Control Register 15 14 13 12 11 Reserved 10 9 SD16XDIV 8 SD16LP r0 r0 r0 r0 rw−0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 SD16 VMIDON REFON SD16OVIE Reserved rw−0 rw−0 rw−0 r0 SD16DIVx rw−0 rw−0 SD16SSELx rw−0 rw−0 SD16 Reserved Bits 15-12 Reserved SD16XDIV Bits 11-9 SD16_A clock divider 000 /1 001 /3 010 /16 011 /48 1xx Reserved SD16LP Bit 8 Low power mode.
SD16_A Registers SD16CCTL0, SD16_A Control Register 0 15 14 Reserved 13 SD16BUFx 12 11 10 SD16UNI SD16XOSR SD16SNGL 9 8 SD16OSRx r0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 SD16 LSBTOG SD16 LSBACC SD16 OVIFG SD16DF SD16IE SD16IFG SD16SC Reserved rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r−0 Reserved Bit 15 Reserved SD16BUF Bits 14−13 High impedance input buffer mode 00 Buffer disabled 01 Slow speed/current 10 Medium speed/current 11 High speed/current SD
SD16_A Registers SD16 LSBACC Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the SD16_A conversion result. 0 SD16MEMx contains the most significant 16-bits of the conversion. 1 SD16MEMx contains the least significant 16-bits of the conversion.
SD16_A Registers SD16INCTL0, SD16_A Input Control Register 7 6 5 SD16INTDLYx rw−0 rw−0 4 3 2 SD16GAINx rw−0 rw−0 1 0 SD16INCHx rw−0 rw−0 rw−0 rw−0 SD16 INTDLYx Bits 7-6 Interrupt delay generation after conversion start. These bits select the delay for the first interrupt after conversion start.
SD16_A Registers SD16MEM0, SD16_A Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 r r r Conversion Results r Conversion Result r Bits 15-0 r r r Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit.
SD16_A Registers SD16IV, SD16_A Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 r0 r0 r0 SD16IVx Bits 15-0 SD16_A r−0 r−0 0 r−0 r−0 r0 SD16_A interrupt vector value SD16IV Contents 22-20 SD16IVx Interrupt Source Interrupt Flag 000h No interrupt pending − 002h SD16MEMx overflow SD16CCTLx SD16OVIFG 004h SD16_A Interrupt SD16CCTL0 SD16IFG 006h Reserved − 008h Reserved − 00Ah Reserv
Chapter 23 DAC12 The DAC12 module is a 12-bit, voltage output digital-to-analog converter. This chapter describes the DAC12. Two DAC12 modules are implemented in the MSP430FG43x devices. Only DAC12_0 is implemented in MSP430x42x0 devices. Topic Page 23.1 DAC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 DAC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3 DAC12 Registers . . . . .
DAC12 Introduction 23.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
DAC12 Introduction Figure 23−1. DAC12 Block Diagram Ve REF+ VREF+ To ADC12 module 2.5V or 1.
DAC12 Introduction Figure 23−2. DAC12 Block Diagram For MSPx42x0 Devices V REF 1.
DAC12 Operation 23.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 23.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using the DAC12RES bit. The full-scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit. This feature allows the user to control the dynamic range of the DAC12.
DAC12 Operation 23.2.2 DAC12 Reference On MSP430FG43x devices, the reference for the DAC12 is configured to use either an external reference voltage or the internal 1.5-V/2.5-V reference from the ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1} the VREF+ signal is used as the reference and when DAC12SREFx = {2,3} the VeREF+ signal is used as the reference. On MSP430x42x0 devices, the reference for the DAC12 is configured to use AVCC, an external reference voltage, or the 1.
DAC12 Operation 23.2.4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2’s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 23−3. Figure 23−3.
DAC12 Operation 23.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the offset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so. The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 23−5. Figure 23−5.
DAC12 Operation 23.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event. On the MSP430FG43x devices, DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0. The DAC12GRP bit of DAC12_1 is don’t care.
DAC12 Operation 23.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller. Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt. The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch. When DAC12LSELx = 0, the DAC12IFG flag is not set. A set DAC12IFG bit indicates that the DAC12 is ready for new data.
DAC12 Registers 23.3 DAC12 Registers The DAC12 registers are listed in Table 23−2. Table 23−2.
DAC12 Registers DAC12_xCTL, DAC12 Control Register 15 14 DAC12OPS 13 DAC12SREFx 12 DAC12RES 11 10 DAC12LSELx 9 8 DAC12 CALON DAC12IR rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DAC12DF DAC12IE DAC12IFG DAC12ENC DAC12 GRP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DAC12AMPx rw−(0) rw−(0) rw−(0) Modifiable only when DAC12ENC = 0 DAC12OPS Bit 15 DAC12 output select for MSP430FG43x and MSP430x42x0 devices.
DAC12 Registers DAC12 CALON Bit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes. 0 Calibration is not active 1 Initiate calibration/calibration in progress DAC12IR Bit 8 DAC12 input range. This bit sets the reference input and voltage output range. 0 DAC12 full-scale output = 3x reference voltage 1 DAC12 full-scale output = 1x reference voltage DAC12 AMPx Bits 7-5 DAC12 amplifier setting.
DAC12 Registers DAC12_xDAT, DAC12 Data Register 15 14 13 12 11 0 0 0 0 r(0) r(0) r(0) r(0) rw−(0) 7 6 5 4 10 9 8 rw−(0) rw−(0) rw−(0) 3 2 1 0 rw−(0) rw−(0) rw−(0) rw−(0) DAC12 Data DAC12 Data rw−(0) Unused rw−(0) Bits 15-12 DAC12 Data Bits rw−(0) rw−(0) Unused. These bits are always 0 and do not affect the DAC12 core. DAC12 data 11-0 DAC12 Data Format 23-14 DAC12 DAC12 Data 12-bit binary The DAC12 data are right-justified. Bit 11 is the MSB.
Chapter 24 The Scan IF peripheral automatically scans sensors and measures linear or rotational motion. This chapter describes the Scan interface. The Scan IF is implemented in the MSP430FW42x devices. Topic Page 24.1 Scan IF Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 Scan IF Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.3 Scan IF Registers . . . . . . . . . . . . . . . . .
Scan IF Introduction 24.1 Scan IF Introduction The Scan IF module is used to automatically measure linear or rotational motion with the lowest possible power consumption. The Scan IF consists of three blocks: the analog front end (AFE), the processing state machine (PSM), and the timing state machine (TSM). The analog front end stimulates the sensors, senses the signal levels and converts them into their digital representation. The digital signals are passed into the processing state machine.
Scan IF Introduction Figure 24−1.
Scan IF Operation 24.2 Scan IF Operation The Scan IF is configured with user software. The setup and operation of the Scan IF is discussed in the following sections. 24.2.1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement. The analog front end is automatically controlled by the timing state machine according to the information in the timing state machine table. The analog front end block diagram is shown in Figure 24−2.
Scan IF Operation Figure 24−2.
Scan IF Operation Excitation The excitation circuitry is used to excite the LC sensors or to power the resistor dividers. The excitation circuitry is shown in Figure 24−3 for one LC sensor connected. When the SIFTEN bit is set and the SIFSH bit is cleared the excitation circuitry is enabled and the sample-and-hold circuitry is disabled.
Scan IF Operation Figure 24−3.
Scan IF Operation Sample-And-Hold The sample-and-hold is used to sample the sensor voltage to be measured. The sample-and-hold circuitry is shown in Figure 24−3. When SIFSH = 1 and SIFTEN = 0 the sample-and-hold circuitry is enabled and the excitation circuitry and mid-voltage generator are disabled. The sample-and-hold is used for resistive dividers or for other analog signals that should be sampled. Up to four resistor dividers can be connected to SIFCHx and SIFCOM.
Scan IF Operation Direct Analog And Digital Inputs By setting the SIFCAX bit, external analog or digital signals can be connected directly to the comparator through the SIFCIx inputs. This allows measurement capabilities for optical encoders and other sensors. Comparator Input Selection And Output Bit Selection The SIFCAX and SIFSH bits select between the SIFCIx channels and the SIFCHx channels for the comparator input as described in Table 24−1. Table 24−1.
Scan IF Operation When SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIx channels and the SIFCI input allowing storage of the comparator output for one input signal into the four output bits SIF0OUT - SIF3OUT. This can be used to observe the envelope function of sensors. The output logic is enabled by the SIFRSON(tsm) signal. When the comparator output is high while SIFRSON = 1, an internal latch is set. Otherwise the latch is reset.
Scan IF Operation Comparator and DAC The analog input signals are converted into digital signals by the comparator and the programmable 10-bit DAC. The comparator compares the selected analog signal to a reference voltage generated by the DAC. If the voltage is above the reference the comparator output will be high. Otherwise it will be low. The comparator output can be inverted by setting SIFCAINV.
Scan IF Operation For each input there are two DAC registers to set the reference level as listed in Table 24−3. Together with the last stored output of the comparator, SIFxOUT, the two levels can be used as an analog hysteresis as shown in Figure 24−6. The individual settings for the four inputs can be used to compensate for mismatches between the sensors. Table 24−3.
Scan IF Operation Internal Signal Connections to Timer1_A5 The outputs of the analog front end are connected to 3 different capture/compare registers of Timer1_A5. The output stage of the analog front end, shown in Figure 24−7. provides two different modes that are selected by the SIFCS bit and provides the SIFOx signals to Timer1_A5. See the device-specific datasheet for connection of these signals. Figure 24−7.
Scan IF Operation 24.2.2 Scan IF Timing State Machine The TSM is a sequential state machine that cycles through the SIFTSMx registers and controls the analog front end and sensor excitation automatically with no CPU intervention. The states are defined within a 24 x 16-bit memory, SIFTSM0 to SIFTSM23. The SIFEN bit enables the TSM. When SIFEN = 0, the ACLK input divider, the TSM start flip-flop, and the TSM outputs are reset and the internal oscillator is stopped.
Scan IF Operation Figure 24−8. Timing State Machine Block Diagram SIFDIV3Ax SIFDIV2x SIFDIV3Bx 3 ACLK 3 Set_SIFIFG2 Divider /2 ..
Scan IF Operation TSM Operation The TSM state machine automatically starts and re-starts periodically based on a divided ACLK start signal selected with the SIFDIV2x bits the SIFDIV3Ax and SIFDIV3Bx bits when SIFTSMRP = 0. For example, if SIFDIV3A and SIFDIV3B are configured to 270 ACLK cycles, then the TSM automatically starts every 270 ACLK cycles. When SIFTSMRP = 1 the TSM starts immediately with the SIFSTM0 state with the next ACLK cycle after encountering a state with a set SIFSTOP bit.
Scan IF Operation TSM State Clock Source Select The TSM clock source is individually configurable for each state. The TSM can be clocked from ACLK or a high frequency clock selected with the SIFACLK bit. When SIFACLK = 1, ACLK is used for the state, and when SIFACLK = 0, the high frequency clock is used. The high frequency clock can be sourced from SMCLK or the TSM internal oscillator, selected by the SIFCLKEN bit. The high-frequency clock can be divided by 1,2,4 or 8 with SIFDIV1x bits.
Scan IF Operation TSM Test Cycles For calibration purposes, to detect sensor drift, or to measure signals other than the sensor signals, a test cycle may be inserted between TSM cycles by setting the SIFTESTD bit. The time between the TSM cycles is not altered by the test cycle insertion as shown in Figure 24−9. At the end of the test cycle the SIFTESTD bit is automatically cleared. The TESTDX signal is active during the test cycle to control input and output channel selection.
Scan IF Operation TSM Example Figure 24−10 shows an example for a TSM sequence. The TSMx register values for the example are shown in Table 24−6. ACLK and SIFCLK are not drawn to scale. The TSM sequence starts with SIFTSM0 and ends with a set SIFSTOP bit in SIFTSM9. Only the SIFTSM5 to SIFTSM9 states are shown. Table 24−6.
Scan IF Operation 24.2.3 Scan IF Processing State Machine The PSM is a programmable state machine used to determine rotation and direction with its state table stored within MSP430 memory (flash, ROM, or RAM). The processing state machine measures rotation and controls interrupt generation based on the inputs from the timing state machine and the analog front-end. The PSM vector SIFPSMV must to be initialized to point to the PSM state table.
Scan IF Operation Figure 24−11.Scan IF Processing State Machine Block Diagram SIFS1x SIF0OUT 00 SIF1OUT 01 SIF2OUT 10 SIF3OUT 11 SIFS2x 00 01 10 State Latch MSP430 Memory Range S1 S2 Output Latch 11 State Table SIFQ6EN Q0 Q7 . . .
Scan IF Operation The current-state and next-state logic are reset while the Scan IF is disabled. One of the bytes stored at addresses SIFPSMV to SIFPSMV + 3 will be loaded first depending on the S1 and S2 signals when the Scan IF is enabled. Signals S1 and S2 form a 2-bit offset added to the SIFPSMV contents to determine the first byte loaded to the PSM output latch. For example, when S2 = 1, and S1 = 0, the first byte loaded by the PSM will be at the address SIFPSMV + 2.
Scan IF Operation PSM Counters The PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updated with Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be read via the SIFCNT register. If the SIFCNTRST bit is set, each read access will reset the counters, otherwise the counters remain unchanged when read. If a count event occurs during a read access the count is postponed until the end of the read access but multiple count events during a read access will increment the counters only once.
Scan IF Operation Simplest State Machine Figure 24−12 shows the simplest state machine that can be realized with the PSM. The following code shows the corresponding state table and the PSM initialization. Figure 24−12.
Scan IF Operation If the PSM is in state 01 of the simplest state machine and the PSM has loaded the corresponding byte at index 01h of the state table: Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 0 For this example, S1 and S2 are set at the end of the next TSM sequence.
Scan IF Operation 24.2.4 Scan IF Debug Register The Scan IF peripheral has a SIFDEBUG register for debugging and development. Only the lower two bits should be written when writing to the SIFDEBUG register and only MOV instructions should be used write to SIFDEBUG. After writing the lower two bits, reading the SIFDEBUG contents gives the user different information. After writing 00h to SIFDEBUG, reading SIFDEBUG shows the last address read by the PSM.
Scan IF Operation 24.2.5 Scan IF Interrupts The Scan IF has one interrupt vector for seven interrupt flags listed in Table 24−7. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt. The interrupt flags are not automatically cleared. They must be cleared with software. Table 24−7.
Scan IF Operation 24.2.6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a damping material to measure rotation. Rotation is measured with LC sensors by exciting the sensors and observing the resulting oscillation. The oscillation is either damped or un-damped by the rotating disk.
Scan IF Operation 24.2.6.1 LC-Sensor Oscillation Test The oscillation test tests if the amplitude of the oscillation after sensor excitation is above a reference level. The DAC is used to set the reference level for the comparator, and the comparator detects if the LC sensor oscillations are above or below the reference level. If the oscillations are above the reference level, the comparator will output a pulse train corresponding to the oscillations and the selected AFE output bit will 1.
Scan IF Operation 24.2.6.2 LC-Sensor Envelope Test The envelop test measures the decay time of the oscillations after sensor excitation. The oscillation envelope is created by the diodes and RC filters. The DAC is used to set the reference level for the comparator, and the comparator detects if the oscillation envelop is above or below the reference level.
Scan IF Operation Figure 24−17.
Scan IF Operation 24.2.7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation. The damping material and magnets modify the electrical behavior of the sensor so that rotation and direction can be detected. Rotation is measured with resistive sensors by connecting the resistor dividers to ground for a short time allowing current flow through the dividers. The resistors are affected by the rotating disc creating different divider voltages.
Scan IF Operation 24.2.8 Quadrature Decoding The Scan IF can be used to decode quadrature-encoded signals. Signals that are 90° out of phase with each other are said to be in quadrature. To Create the signals, two sensors are positioned depending on the slotting, or coating of the encoder disk. Figure 24−19 shows two examples for the sensor positions and a quadrature-encoded signal waveform. Figure 24−19.
Scan IF Operation Figure 24−20. Quadrature Decoding State Diagram 00 00 −1 +1 10 10 01 01 11 11 Correct State Transitions Erroneous State Transitions To transfer the state encoding into counts it is necessary to decide what fraction of the rotation should be counted and on what state transitions. In this example only full rotations will be counted on the transition from state 00 to 01 or 10 using a 180° disk with the sensors 90° apart.
Scan IF Registers 24.3 Scan IF Registers The Scan IF registers are listed in Table 24−9. Table 24−9.
Scan IF Registers SIFDEBUG, Scan IF Debug Register, Write Mode 15 14 13 12 11 10 9 8 Reserved w w w w w w w w 7 6 5 4 3 2 1 0 Reserved w Reserved w Bits 15-2 w SIFDEBUGx w w w w w Reserved. Must be written as zero. SIFDEBUGx Bits SIFDEBUG register mode. Writing these bits selects the read-mode of the SIFDEBUG register. SIFDEBUG must be written with MOV instructions only.
Scan IF Registers SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written 15 14 13 12 11 0 0 0 r r r r r 7 6 5 4 3 10 9 8 r r r 2 1 0 r r r Index Of TSM Register PSM Bits Q7 − Q0 r r r r r Unused Bits 15-13 Unused. After 01h is written to SIFDEBUG, these bits are always read as zero. TSM Index Bits 12-8 When SIFDEBUG is read, after 01h is written to it, these bits show the TSM register pointer index.
Scan IF Registers SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written 15 14 13 12 Active DAC Register 0 11 10 0 0 9 8 DAC Data r r r r r r r r 7 6 5 4 3 2 1 0 r r r r DAC Data r r r r Unused Bit 15 Unused. After 03h is written to SIFDEBUG, this bit is always read as zero. DAC Register Bits 14-12 When SIFDEBUG is read, after 03h is written to it, these bits show which DAC register is currently selected to control the DAC. Unused Bits 11-10 Unused.
Scan IF Registers SIFCNT, Scan IF Counter Register 15 14 13 12 11 10 9 8 SIFCNT2x r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) 7 6 5 4 3 2 1 0 r−(0) r−(0) r−(0) r−(0) SIFCNT1x r−(0) r−(0) r−(0) r−(0) SIFCNT2x Bits 15-8 SIFCNT2. These bits are the SIFCNT2 counter. SIFCNT2 is reset when SIFEN = 0 or if read when SIFCNTRST = 1. SIFCNT1x Bits 7-0 SIFCNT1. These bits are the SIFCNT1 counter. SIFCNT1 is reset when SIFEN = 0 or if read when SIFCNTRST = 1.
Scan IF Registers SIFCTL1, Scan IF Control Register 1 15 14 13 12 11 10 9 8 SIFIE6 SIFIE5 SIFIE4 SIFIE3 SIFIE2 SIFIE1 SIFIE0 SIFIFG6 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFIFG5 SIFIFG4 SIFIFG3 SIFIFG2 SIFIFG1 SIFIFG0 SIFTESTD SIFEN rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFIEx Bits 15-9 Interrupt Enable. These bits enable or disable the interrupt request for the SIFIFGx bits.
Scan IF Registers SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by the SIFIFGSETx bits. SIFIFG0 must be reset with software. 0 No interrupt pending 1 Interrupt pending SIFTESTD Bit 1 Test cycle insertion. Setting this bit inserts a test cycle between TSM cycles. SIFTESTD is automatically reset at the end of the test cycle. 0 No test cycle inserted 1 Test cycle inserted between TSM cycles. SIFEN Bit 0 Scan interface enable.
Scan IF Registers SIFCTL2, Scan IF Control Register 2 15 14 13 12 11 10 9 8 SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFSH SIFTEN SIFTCH1 OUT SIFTCH0 OUT rw−(0) rw−(0) rw−(0) rw−(0) SIFTCH1x rw−(0) rw−(0) SIFTCH0x rw−(0) rw−(0) SIFDACON Bit 15 DAC on. Setting this bit turns the DAC on regardless of the TSM control. 0 The DAC is controlled by the TSM.
Scan IF Registers SIFVCC2 Bit 8 Mid-voltage generator 0 AVCC/2 generator is off 1 AVCC/2 generator is on if SIFSH = 0 SIFSH Bit 7 Sample-and-hold enable 0 Sample-and-hold is disabled 1 Sample-and-hold is enabled SIFTEN Bit 6 Excitation enable 0 Excitation circuitry is disabled 1 Excitation circuitry is enabled SIFTCH1x Bits 5-4 These bits select the comparator input for test channel 1.
Scan IF Registers SIFCTL3, Scan IF Control Register 3 15 14 13 SIFS2x 12 11 SIFS1x 10 9 SIFIS2x 8 SIFIS1x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIF3OUT SIF2OUT SIF1OUT SIF0OUT r−(0) r−(0) r−(0) r−(0) SIFCS rw−(0) SIFIFGSETx rw−(0) rw−(0) rw−(0) SIFS2x Bits 15-14 S2 source select. These bits select the S2 source for the PSM when SIFCS = 1. 00 SIF0OUT is the S2 source. 01 SIF1OUT is the S2 source. 10 SIF2OUT is the S2 source.
Scan IF Registers SIFIFGSETx Bits 6-4 SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set. 000 SIFIFG0 is set when SIF0OUT is set. 001 SIFIFG0 is set when SIF0OUT is reset. 010 SIFIFG0 is set when SIF1OUT is set. 011 SIFIFG0 is set when SIF1OUT is reset. 100 SIFIFG0 is set when SIF2OUT is set. 101 SIFIFG0 is set when SIF2OUT is reset. 110 SIFIFG0 is set when SIF3OUT is set. 111 SIFIFG0 is set when SIF3OUT is reset.
Scan IF Registers SIFCTL4, Scan IF Control Register 4 15 14 13 12 11 10 SIFCNTRST SIFCNT2EN SIFCNT1 ENM SIFCNT1 ENP SIFQ7EN SIFQ6EN rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFDIV3Bx rw−(0) SIFDIV3Ax rw−(0) rw−(0) SIFDIV2x rw−(0) rw−(0) rw−(0) 9 8 SIFDIV3Bx SIFDIV1x rw−(0) rw−(0) SIFCNTRST Bit 15 Counter reset. Setting this bit enables the SIFCNT register to be reset when it is read.
Scan IF Registers SIFDIV3Bx Bits 9-7 TSM start trigger ACLK divider. These bits together with the SIFDIV3Ax bits select the division rate for the TSM start trigger. SIFDIV3Ax Bits 6-4 TSM start trigger ACLK divider. These bits together with the SIFDIV3Bx bits select the division rate for the TSM start trigger.
Scan IF Registers SIFCTL5, Scan IF Control Register 5 15 14 13 12 11 10 9 8 SIFCNT3x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFFNOM SIFCLKG ON SIFCLKEN rw−(0) rw−(0) rw−(0) SIFTSMRP rw−(0) SIFCLFQx rw−(1) rw−(0) rw−(0) rw−(0) SIFCNT3x Bits 15-8 Internal oscillator counter.
Scan IF Registers SIFDACRx, Digital-To-Analog Converter Registers 15 14 13 12 11 10 9 8 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 rw rw 7 6 5 4 3 2 1 0 rw rw rw rw DAC Data DAC Data rw rw rw rw Unused Bits 15-10 Unused. These bits are always read as zero, and when written, do not affect the DAC output.
Scan IF Registers SIFTSMx, Scan IF Timing State Machine Registers 15 14 13 12 11 SIFREPEATx 10 9 8 SIFACLK SIFSTOP SIFDAC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFTESTS1 SIFRSON SIFCLKON SIFCA SIFEX SIFLCEN rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCHx rw−(0) rw−(0) SIF REPEATx Bits 15-11 These bits together with the SIFACLK bit configure the duration of this state. SIFREPEATx selects the number of clock cycles for this state.
Scan IF Registers SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock source on for this state when SIFACLK = 1, even though the high frequency clock is not used for the TSM. When the high-frequency clock is sourced from the DCO, the DCO is forced on for this state, regardless of the MSP430 low-power mode. 0 High-frequency clock is off for this state when SIFACLK = 1 1 High-frequency clock is on for this state when SIFACLK = 1 SIFCA Bit 4 TSM comparator on.
Scan IF Registers Processing State Machine Table Entry (MSP430 Memory Location) 7 6 5 4 3 2 1 0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Bit 7 When Q7 = 1, SIFIFG6 will be set. When SIFQ6EN = 1 and SIFQ7EN = 1 and Q7 = 1, the PSM proceeds to the next state immediately, regardless of the SIFSTOP(tsm) signal and Q7 is used in the next-state calculation. Q6 Bit 6 When Q6 = 1, SIFIFG5 will be set. When SIFQ6EN = 1, Q6 will be used in the next-state calculation. Q5 Bit 5 Bit 5 of the next state.
